Ettus Research LLC

01/07/2013

05:27 am fpga Bug #596 (Rejected): ram_2port.v flopping order

Was not a problem.

05:26 am fpga Bug #595 (Rejected): fifo_2clock_cascade reset

Not a problem, won't fix

02/17/2012

03:10 am uhd Revision 2ad9e0ad: dsp_engine: fix for upper/lower swap, and odd length packets

03:10 am fpga Revision 2ad9e0ad: dsp_engine: fix for upper/lower swap, and odd length packets

02/03/2012

04:59 am uhd Revision ae1997f8: power_trig: test code for power trigger

04:59 am fpga Revision ae1997f8: power_trig: test code for power trigger

01:57 am fpga Revision 1ce83a07: power_trig: first cut at power trigger with fixed delay

02/02/2012

07:00 pm fpga Revision 17f5776c: dsp_rework: testbench enhancements

02/01/2012

01:22 am fpga Revision 7b69532a: dsp_rework: handle longer headers

01/31/2012

08:06 pm fpga Revision 08b60ada: dsp_rework: more thorough test