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| 1 | ace44890 | Josh Blum | ######################################################################## |
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| 2 | ## Welcome to the USRP FPGA source code tree |
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| 3 | ######################################################################## |
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| 4 | |||
| 5 | usrp1/ |
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| 6 | |||
| 7 | Description: generation 1 products |
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| 8 | |||
| 9 | Devices: USRP classic only |
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| 10 | |||
| 11 | Tools: Quartus from Altera |
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| 12 | |||
| 13 | Project file: usrp1/toplevel/usrp_std/ |
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| 14 | |||
| 15 | usrp2/ |
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| 16 | |||
| 17 | Description: generation 2 products |
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| 18 | |||
| 19 | Devices: USRP2, N2XX, B100, E1XX |
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| 20 | |||
| 21 | Tools: ISE from Xilinx, GNU make |
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| 22 | |||
| 23 | Build Instructions: |
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| 24 | 1) ensure that xtclsh is in the $PATH |
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| 25 | 2) cd usrp2/top/<project-directory> |
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| 26 | 3) make -f Makefile.<device> bin |
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| 27 | 4) bin file in build-<device>/*.bin |
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| 28 | |||
| 29 | ######################################################################## |
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| 30 | ## Customizing the DSP |
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| 31 | ######################################################################## |
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| 32 | |||
| 33 | As part of the USRP FPGA build-framework, |
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| 34 | there are several convenient places for users to insert |
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| 35 | custom DSP modules into the transmit and receive chains. |
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| 36 | |||
| 37 | * before the DDC module |
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| 38 | * after the DDC module |
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| 39 | * replace the DDC module |
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| 40 | * before the DUC module |
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| 41 | * after the DUC module |
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| 42 | * replace of the DUC module |
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| 43 | * as an RX packet engine |
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| 44 | * as an TX packet engine |
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| 45 | |||
| 46 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
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| 47 | Customizing the top level makefile |
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| 48 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
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| 49 | Each USRP device has a makefile associated with it. |
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| 50 | This makefile contains all of the necessary build rules. |
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| 51 | When making a customized FPGA design, |
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| 52 | start by copying the current makefile for your device. |
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| 53 | Makefiles can be found in the usrp2/top/<dir>/Makefile.* |
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| 54 | |||
| 55 | Edit your new makefile: |
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| 56 | * set BUILD_DIR to a unique directory name |
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| 57 | * set CUSTOM_SRCS for your verilog sources |
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| 58 | * set CUSTOM_DEFS (see section below) |
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| 59 | |||
| 60 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
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| 61 | Inserting custom modules |
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| 62 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
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| 63 | CUSTOM_DEFS is a string of space-separate key-value pairs. |
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| 64 | Set the CUSTOM_DEFS variable so the FPGA fabric glue |
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| 65 | will substitute your custom modules into the DSP chain. |
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| 66 | |||
| 67 | Example: |
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| 68 | CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine" |
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| 69 | Where my_tx_engine and my_rx_engine are the names of custom verilog modules. |
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| 70 | |||
| 71 | The following module definition keys are possible (X is a DSP number): |
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| 72 | |||
| 73 | * TX_ENG<X>_MODULE: set the module for the transmit chain engine. |
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| 74 | * RX_ENG<X>_MODULE: set the module for the receive chain engine. |
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| 75 | * RX_DSP<X>_MODULE: set the module for the transmit dsp chain. |
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| 76 | * TX_DSP<X>_MODULE: set the module for the receive dsp chain. |
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| 77 | |||
| 78 | Examples of custom modules can be found in usrp2/custom/*.v |