Revision fd4bdced

b/usrp2/control_lib/settings_bus.v
10 10 
     input wb_stb_i,
11 11 
     input wb_we_i,
12 12 
     output reg wb_ack_o,
13 
     output reg strobe,
13 
     output strobe,
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     output reg [7:0] addr,
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     output reg [31:0] data);
16 16 

  		




  ......




  19
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   always @(posedge wb_clk)


  		




  20
  20
  
    
     if(wb_rst)


  		




  21
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       begin


  		




  22
  
  
    
	  strobe <= 1'b0;


  		




  
  22
  
    
	  stb_int <= 1'b0;


  		




  23
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	  addr <= 8'd0;


  		




  24
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	  data <= 32'd0;


  		




  25
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       end


  		




  26
  
  
    
     else if(wb_we_i & wb_stb_i & ~wb_ack_o)


  		




  
  26
  
    
     else if(wb_we_i & wb_stb_i)


  		




  27
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       begin


  		




  28
  
  
    
	  strobe <= 1'b1;


  		




  
  28
  
    
	  stb_int <= 1'b1;


  		




  29
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	  addr <= wb_adr_i[9:2];


  		




  30
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	  data <= wb_dat_i;


  		




  31
  31
  
    
       end


  		




  32
  32
  
    
     else


  		




  33
  
  
    
       strobe <= 1'b0;


  		




  
  33
  
    
       stb_int <= 1'b0;


  		




  34
  34
  
    

  		




  35
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   always @(posedge wb_clk)


  		




  36
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     if(wb_rst)


  		




  ......




  38
  38
  
    
     else


  		




  39
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       wb_ack_o <= wb_stb_i & ~wb_ack_o;


  		




  40
  40
  
    

  		




  
  41
  
    
   always @(posedge wb_clk)


  		




  
  42
  
    
     stb_int_d1 <= stb_int;


  		




  
  43
  
    

  		




  
  44
  
    
   //assign strobe = stb_int & ~stb_int_d1;


  		




  
  45
  
    
   assign strobe = stb_int & wb_ack_o;


  		




  
  46
  
    
          


  		




  41
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endmodule // settings_bus


  		




  
  48
  
    

  		












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