Revision fb1f8e1a
| b/host/lib/usrp/dsp_utils.cpp | ||
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| 30 | 30 |
return std::ceil(std::log(num)/std::log(T(2))); |
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} |
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/*! |
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* 3 2 1 0 |
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
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* +-------------------------------+-------+-------+-------+-------+ |
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* | | DDC0Q | DDC0I | |
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* +-------------------------------+-------+-------+-------+-------+ |
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*/ |
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boost::uint32_t dsp_type1::calc_rx_mux_word(subdev_conn_t subdev_conn){
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switch(subdev_conn){
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case SUBDEV_CONN_COMPLEX_IQ: return (0x1 << 2) | (0x0 << 0); //DDC0Q=ADC1, DDC0I=ADC0
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case SUBDEV_CONN_COMPLEX_QI: return (0x0 << 2) | (0x1 << 0); //DDC0Q=ADC0, DDC0I=ADC1
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case SUBDEV_CONN_REAL_I: return (0x3 << 2) | (0x0 << 0); //DDC0Q=ZERO, DDC0I=ADC0
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case SUBDEV_CONN_REAL_Q: return (0x1 << 2) | (0x3 << 0); //DDC0Q=ADC1, DDC0I=ZERO
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case SUBDEV_CONN_COMPLEX_IQ: return (0x1 << 4) | (0x0 << 0); //DDC0Q=ADC0Q, DDC0I=ADC0I
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case SUBDEV_CONN_COMPLEX_QI: return (0x0 << 4) | (0x1 << 0); //DDC0Q=ADC0I, DDC0I=ADC0Q
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case SUBDEV_CONN_REAL_I: return (0xf << 4) | (0x0 << 0); //DDC0Q=ZERO, DDC0I=ADC0I
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case SUBDEV_CONN_REAL_Q: return (0x1 << 4) | (0xf << 0); //DDC0Q=ADC0Q, DDC0I=ZERO
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default: UHD_THROW_INVALID_CODE_PATH(); |
| 40 | 47 |
} |
| 41 | 48 |
} |
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|
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/*! |
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* 3 2 1 0 |
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
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* +-------------------------------+-------+-------+-------+-------+ |
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* | | DAC0Q | DAC0I | |
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* +-------------------------------+-------+-------+-------+-------+ |
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*/ |
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boost::uint32_t dsp_type1::calc_tx_mux_word(subdev_conn_t subdev_conn){
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switch(subdev_conn){
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case SUBDEV_CONN_COMPLEX_IQ: return (0x1 << 4) | (0x0 << 0); //DAC1=DUC0Q, DAC0=DUC0I
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case SUBDEV_CONN_COMPLEX_QI: return (0x0 << 4) | (0x1 << 0); //DAC1=DUC0I, DAC0=DUC0Q
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case SUBDEV_CONN_REAL_I: return (0xf << 4) | (0x0 << 0); //DAC1=ZERO, DAC0=DUC0I
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case SUBDEV_CONN_REAL_Q: return (0x0 << 4) | (0xf << 0); //DAC1=DUC0I, DAC0=ZERO
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case SUBDEV_CONN_COMPLEX_IQ: return (0x1 << 4) | (0x0 << 0); //DAC0Q=DUC0Q, DAC0I=DUC0I
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case SUBDEV_CONN_COMPLEX_QI: return (0x0 << 4) | (0x1 << 0); //DAC0Q=DUC0I, DAC0I=DUC0Q
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case SUBDEV_CONN_REAL_I: return (0xf << 4) | (0x0 << 0); //DAC0Q=ZERO, DAC0I=DUC0I
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case SUBDEV_CONN_REAL_Q: return (0x0 << 4) | (0xf << 0); //DAC0Q=DUC0I, DAC0I=ZERO
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default: UHD_THROW_INVALID_CODE_PATH(); |
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} |
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} |
| b/host/lib/usrp/usrp2/fw_common.h | ||
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| 33 | 33 |
#endif |
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//fpga and firmware compatibility numbers |
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#define USRP2_FPGA_COMPAT_NUM 1
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#define USRP2_FPGA_COMPAT_NUM 2
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#define USRP2_FW_COMPAT_NUM 6 |
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//used to differentiate control packets over data port |
| b/host/lib/usrp/usrp2/usrp2_regs.hpp | ||
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| 124 | 124 |
#define U2_REG_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) |
| 125 | 125 |
#define U2_REG_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q}
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#define U2_REG_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) |
| 127 |
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/*! |
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* \brief output mux configuration. |
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* |
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* <pre> |
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* 3 2 1 |
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
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* +-------------------------------+-------+-------+-------+-------+ |
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* | | DAC1 | DAC0 | |
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* +-------------------------------+-------+-------+-------+-------+ |
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* |
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* There are N DUCs (1 now) with complex inputs and outputs. |
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* There are two DACs. |
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* |
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* Each 4-bit DACx field specifies the source for the DAC |
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* Each subfield is coded like this: |
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* |
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* 3 2 1 0 |
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* +-------+ |
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* | N | |
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* +-------+ |
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* |
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* N specifies which DUC output is connected to this DAC. |
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* |
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* N which interp output |
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* --- ------------------- |
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* 0 DUC 0 I |
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* 1 DUC 0 Q |
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* 2 DUC 1 I |
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* 3 DUC 1 Q |
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* F All Zeros |
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* |
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* The default value is 0x10 |
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* </pre> |
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*/ |
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#define U2_REG_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) |
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///////////////////////////////////////////////// |
| ... | ... | |
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#define U2_REG_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, |
| 171 | 136 |
// otherwise it is automatic |
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#define U2_REG_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits |
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/*! |
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* \brief input mux configuration. |
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* |
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* This determines which ADC (or constant zero) is connected to |
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* each DDC input. There are N DDCs (1 now). Each has two inputs. |
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* |
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* <pre> |
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* Mux value: |
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* |
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* 3 2 1 |
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
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* +-------+-------+-------+-------+-------+-------+-------+-------+ |
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* | |Q0 |I0 | |
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* +-------+-------+-------+-------+-------+-------+-------+-------+ |
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* |
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* Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) |
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* Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero) |
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* |
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* The default value is 0x4 |
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* </pre> |
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*/ |
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#define U2_REG_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v |
| 195 | 139 |
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//////////////////////////////////////////////// |
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