/usrp2/models/RAMB16_S36_S36.v - Annotate - uhd - Ettus Research LLC

jcorgan

// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $

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///////////////////////////////////////////////////////////////////////////////

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// Copyright (c) 1995/2005 Xilinx, Inc.

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// All Right Reserved.

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///////////////////////////////////////////////////////////////////////////////

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//   ____  ____

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//  /   /\/   /

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// /___/  \  /    Vendor : Xilinx

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// \   \   \/     Version : 10.1

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//  \   \         Description : Xilinx Functional Simulation Library Component

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//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM

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// /___/   /\     Filename : RAMB16_S36_S36.v

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// \   \  /  \    Timestamp : Thu Mar 10 16:43:36 PST 2005

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//  \___\/\___\

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//

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// Revision:

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//    03/23/04 - Initial version.

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// End Revision

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`ifdef legacy_model

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`timescale  1 ps / 1 ps

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module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);

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    parameter INIT_A = 36'h0;

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    parameter INIT_B = 36'h0;

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    parameter SRVAL_A = 36'h0;

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    parameter SRVAL_B = 36'h0;

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    parameter WRITE_MODE_A = "WRITE_FIRST";

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    parameter WRITE_MODE_B = "WRITE_FIRST";

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    parameter SIM_COLLISION_CHECK = "ALL";

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    localparam SETUP_ALL = 1000;

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    localparam SETUP_READ_FIRST = 3000;

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    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

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    output [31:0] DOA;

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    output [3:0] DOPA;

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    reg [31:0] doa_out;

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    reg [3:0] dopa_out;

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    wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31;

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    wire dopa0_out, dopa1_out, dopa2_out, dopa3_out;

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    input [8:0] ADDRA;

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    input [31:0] DIA;

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    input [3:0] DIPA;

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    input ENA, CLKA, WEA, SSRA;

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    output [31:0] DOB;

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    output [3:0] DOPB;

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    reg [31:0] dob_out;

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    reg [3:0] dopb_out;

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    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;

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    wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;

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    input [8:0] ADDRB;

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    input [31:0] DIB;

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    input [3:0] DIPB;

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    input ENB, CLKB, WEB, SSRB;

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    reg [18431:0] mem;

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    reg [8:0] count;

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    reg [1:0] wr_mode_a, wr_mode_b;

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    reg [5:0] dmi, dbi;

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    reg [5:0] pmi, pbi;

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    wire [8:0] addra_int;

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    reg [8:0] addra_reg;

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    wire [31:0] dia_int;

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    wire [3:0] dipa_int;

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    wire ena_int, clka_int, wea_int, ssra_int;

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    reg ena_reg, wea_reg, ssra_reg;

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    wire [8:0] addrb_int;

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    reg [8:0] addrb_reg;

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    wire [31:0] dib_int;

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    wire [3:0] dipb_int;

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    wire enb_int, clkb_int, web_int, ssrb_int;

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    reg display_flag;

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    reg enb_reg, web_reg, ssrb_reg;

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    time time_clka, time_clkb;

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    time time_clka_clkb;

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    time time_clkb_clka;

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    reg setup_all_a_b;

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    reg setup_all_b_a;

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    reg setup_zero;

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    reg setup_rf_a_b;

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    reg setup_rf_b_a;

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    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;

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    reg memory_collision, memory_collision_a_b, memory_collision_b_a;

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    reg address_collision, address_collision_a_b, address_collision_b_a;

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    reg change_clka;

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    reg change_clkb;

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    wire [14:0] data_addra_int;

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    wire [14:0] data_addra_reg;

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    wire [14:0] data_addrb_int;

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    wire [14:0] data_addrb_reg;

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    wire [15:0] parity_addra_int;

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    wire [15:0] parity_addra_reg;

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    wire [15:0] parity_addrb_int;

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    wire [15:0] parity_addrb_reg;

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    tri0 GSR = glbl.GSR;

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    always @(GSR)

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	if (GSR) begin

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	    assign doa_out = INIT_A[31:0];

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	    assign dopa_out = INIT_A[35:32];

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	    assign dob_out = INIT_B[31:0];

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	    assign dopb_out = INIT_B[35:32];

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end

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	else begin

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	    deassign doa_out;

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	    deassign dopa_out;

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	    deassign dob_out;

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	    deassign dopb_out;

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end

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    buf b_doa_out0 (doa_out0, doa_out[0]);

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    buf b_doa_out1 (doa_out1, doa_out[1]);

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    buf b_doa_out2 (doa_out2, doa_out[2]);

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    buf b_doa_out3 (doa_out3, doa_out[3]);

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    buf b_doa_out4 (doa_out4, doa_out[4]);

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    buf b_doa_out5 (doa_out5, doa_out[5]);

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    buf b_doa_out6 (doa_out6, doa_out[6]);

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    buf b_doa_out7 (doa_out7, doa_out[7]);

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    buf b_doa_out8 (doa_out8, doa_out[8]);

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    buf b_doa_out9 (doa_out9, doa_out[9]);

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    buf b_doa_out10 (doa_out10, doa_out[10]);

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    buf b_doa_out11 (doa_out11, doa_out[11]);

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    buf b_doa_out12 (doa_out12, doa_out[12]);

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    buf b_doa_out13 (doa_out13, doa_out[13]);

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    buf b_doa_out14 (doa_out14, doa_out[14]);

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    buf b_doa_out15 (doa_out15, doa_out[15]);

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    buf b_doa_out16 (doa_out16, doa_out[16]);

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    buf b_doa_out17 (doa_out17, doa_out[17]);

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    buf b_doa_out18 (doa_out18, doa_out[18]);

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    buf b_doa_out19 (doa_out19, doa_out[19]);

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    buf b_doa_out20 (doa_out20, doa_out[20]);

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    buf b_doa_out21 (doa_out21, doa_out[21]);

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    buf b_doa_out22 (doa_out22, doa_out[22]);

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    buf b_doa_out23 (doa_out23, doa_out[23]);

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    buf b_doa_out24 (doa_out24, doa_out[24]);

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    buf b_doa_out25 (doa_out25, doa_out[25]);

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    buf b_doa_out26 (doa_out26, doa_out[26]);

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    buf b_doa_out27 (doa_out27, doa_out[27]);

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    buf b_doa_out28 (doa_out28, doa_out[28]);

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    buf b_doa_out29 (doa_out29, doa_out[29]);

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    buf b_doa_out30 (doa_out30, doa_out[30]);

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    buf b_doa_out31 (doa_out31, doa_out[31]);

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    buf b_dopa_out0 (dopa_out0, dopa_out[0]);

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    buf b_dopa_out1 (dopa_out1, dopa_out[1]);

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    buf b_dopa_out2 (dopa_out2, dopa_out[2]);

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    buf b_dopa_out3 (dopa_out3, dopa_out[3]);

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    buf b_dob_out0 (dob_out0, dob_out[0]);

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    buf b_dob_out1 (dob_out1, dob_out[1]);

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    buf b_dob_out2 (dob_out2, dob_out[2]);

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    buf b_dob_out3 (dob_out3, dob_out[3]);

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    buf b_dob_out4 (dob_out4, dob_out[4]);

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    buf b_dob_out5 (dob_out5, dob_out[5]);

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    buf b_dob_out6 (dob_out6, dob_out[6]);

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    buf b_dob_out7 (dob_out7, dob_out[7]);

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    buf b_dob_out8 (dob_out8, dob_out[8]);

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    buf b_dob_out9 (dob_out9, dob_out[9]);

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    buf b_dob_out10 (dob_out10, dob_out[10]);

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    buf b_dob_out11 (dob_out11, dob_out[11]);

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    buf b_dob_out12 (dob_out12, dob_out[12]);

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    buf b_dob_out13 (dob_out13, dob_out[13]);

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    buf b_dob_out14 (dob_out14, dob_out[14]);

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    buf b_dob_out15 (dob_out15, dob_out[15]);

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    buf b_dob_out16 (dob_out16, dob_out[16]);

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    buf b_dob_out17 (dob_out17, dob_out[17]);

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    buf b_dob_out18 (dob_out18, dob_out[18]);

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    buf b_dob_out19 (dob_out19, dob_out[19]);

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    buf b_dob_out20 (dob_out20, dob_out[20]);

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    buf b_dob_out21 (dob_out21, dob_out[21]);

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    buf b_dob_out22 (dob_out22, dob_out[22]);

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    buf b_dob_out23 (dob_out23, dob_out[23]);

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    buf b_dob_out24 (dob_out24, dob_out[24]);

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    buf b_dob_out25 (dob_out25, dob_out[25]);

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    buf b_dob_out26 (dob_out26, dob_out[26]);

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    buf b_dob_out27 (dob_out27, dob_out[27]);

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    buf b_dob_out28 (dob_out28, dob_out[28]);

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    buf b_dob_out29 (dob_out29, dob_out[29]);

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    buf b_dob_out30 (dob_out30, dob_out[30]);

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    buf b_dob_out31 (dob_out31, dob_out[31]);

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    buf b_dopb_out0 (dopb_out0, dopb_out[0]);

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    buf b_dopb_out1 (dopb_out1, dopb_out[1]);

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    buf b_dopb_out2 (dopb_out2, dopb_out[2]);

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    buf b_dopb_out3 (dopb_out3, dopb_out[3]);

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    buf b_doa0 (DOA[0], doa_out0);

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    buf b_doa1 (DOA[1], doa_out1);

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    buf b_doa2 (DOA[2], doa_out2);

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    buf b_doa3 (DOA[3], doa_out3);

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    buf b_doa4 (DOA[4], doa_out4);

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    buf b_doa5 (DOA[5], doa_out5);

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    buf b_doa6 (DOA[6], doa_out6);

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    buf b_doa7 (DOA[7], doa_out7);

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    buf b_doa8 (DOA[8], doa_out8);

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    buf b_doa9 (DOA[9], doa_out9);

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    buf b_doa10 (DOA[10], doa_out10);

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    buf b_doa11 (DOA[11], doa_out11);

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    buf b_doa12 (DOA[12], doa_out12);

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    buf b_doa13 (DOA[13], doa_out13);

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    buf b_doa14 (DOA[14], doa_out14);

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    buf b_doa15 (DOA[15], doa_out15);

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    buf b_doa16 (DOA[16], doa_out16);

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    buf b_doa17 (DOA[17], doa_out17);

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    buf b_doa18 (DOA[18], doa_out18);

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    buf b_doa19 (DOA[19], doa_out19);

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    buf b_doa20 (DOA[20], doa_out20);

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    buf b_doa21 (DOA[21], doa_out21);

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    buf b_doa22 (DOA[22], doa_out22);

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    buf b_doa23 (DOA[23], doa_out23);

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    buf b_doa24 (DOA[24], doa_out24);

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    buf b_doa25 (DOA[25], doa_out25);

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    buf b_doa26 (DOA[26], doa_out26);

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    buf b_doa27 (DOA[27], doa_out27);

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    buf b_doa28 (DOA[28], doa_out28);

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    buf b_doa29 (DOA[29], doa_out29);

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    buf b_doa30 (DOA[30], doa_out30);

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    buf b_doa31 (DOA[31], doa_out31);

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    buf b_dopa0 (DOPA[0], dopa_out0);

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    buf b_dopa1 (DOPA[1], dopa_out1);

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    buf b_dopa2 (DOPA[2], dopa_out2);

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    buf b_dopa3 (DOPA[3], dopa_out3);

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    buf b_dob0 (DOB[0], dob_out0);

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    buf b_dob1 (DOB[1], dob_out1);

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    buf b_dob2 (DOB[2], dob_out2);

306

    buf b_dob3 (DOB[3], dob_out3);

307

    buf b_dob4 (DOB[4], dob_out4);

308

    buf b_dob5 (DOB[5], dob_out5);

309

    buf b_dob6 (DOB[6], dob_out6);

310

    buf b_dob7 (DOB[7], dob_out7);

311

    buf b_dob8 (DOB[8], dob_out8);

312

    buf b_dob9 (DOB[9], dob_out9);

313

    buf b_dob10 (DOB[10], dob_out10);

314

    buf b_dob11 (DOB[11], dob_out11);

315

    buf b_dob12 (DOB[12], dob_out12);

316

    buf b_dob13 (DOB[13], dob_out13);

317

    buf b_dob14 (DOB[14], dob_out14);

318

    buf b_dob15 (DOB[15], dob_out15);

319

    buf b_dob16 (DOB[16], dob_out16);

320

    buf b_dob17 (DOB[17], dob_out17);

321

    buf b_dob18 (DOB[18], dob_out18);

322

    buf b_dob19 (DOB[19], dob_out19);

323

    buf b_dob20 (DOB[20], dob_out20);

324

    buf b_dob21 (DOB[21], dob_out21);

325

    buf b_dob22 (DOB[22], dob_out22);

326

    buf b_dob23 (DOB[23], dob_out23);

327

    buf b_dob24 (DOB[24], dob_out24);

328

    buf b_dob25 (DOB[25], dob_out25);

329

    buf b_dob26 (DOB[26], dob_out26);

330

    buf b_dob27 (DOB[27], dob_out27);

331

    buf b_dob28 (DOB[28], dob_out28);

332

    buf b_dob29 (DOB[29], dob_out29);

333

    buf b_dob30 (DOB[30], dob_out30);

334

    buf b_dob31 (DOB[31], dob_out31);

335

    buf b_dopb0 (DOPB[0], dopb_out0);

336

    buf b_dopb1 (DOPB[1], dopb_out1);

337

    buf b_dopb2 (DOPB[2], dopb_out2);

338

    buf b_dopb3 (DOPB[3], dopb_out3);

339

340

    buf b_addra_0 (addra_int[0], ADDRA[0]);

341

    buf b_addra_1 (addra_int[1], ADDRA[1]);

342

    buf b_addra_2 (addra_int[2], ADDRA[2]);

343

    buf b_addra_3 (addra_int[3], ADDRA[3]);

344

    buf b_addra_4 (addra_int[4], ADDRA[4]);

345

    buf b_addra_5 (addra_int[5], ADDRA[5]);

346

    buf b_addra_6 (addra_int[6], ADDRA[6]);

347

    buf b_addra_7 (addra_int[7], ADDRA[7]);

348

    buf b_addra_8 (addra_int[8], ADDRA[8]);

349

    buf b_dia_0 (dia_int[0], DIA[0]);

350

    buf b_dia_1 (dia_int[1], DIA[1]);

351

    buf b_dia_2 (dia_int[2], DIA[2]);

352

    buf b_dia_3 (dia_int[3], DIA[3]);

353

    buf b_dia_4 (dia_int[4], DIA[4]);

354

    buf b_dia_5 (dia_int[5], DIA[5]);

355

    buf b_dia_6 (dia_int[6], DIA[6]);

356

    buf b_dia_7 (dia_int[7], DIA[7]);

357

    buf b_dia_8 (dia_int[8], DIA[8]);

358

    buf b_dia_9 (dia_int[9], DIA[9]);

359

    buf b_dia_10 (dia_int[10], DIA[10]);

360

    buf b_dia_11 (dia_int[11], DIA[11]);

361

    buf b_dia_12 (dia_int[12], DIA[12]);

362

    buf b_dia_13 (dia_int[13], DIA[13]);

363

    buf b_dia_14 (dia_int[14], DIA[14]);

364

    buf b_dia_15 (dia_int[15], DIA[15]);

365

    buf b_dia_16 (dia_int[16], DIA[16]);

366

    buf b_dia_17 (dia_int[17], DIA[17]);

367

    buf b_dia_18 (dia_int[18], DIA[18]);

368

    buf b_dia_19 (dia_int[19], DIA[19]);

369

    buf b_dia_20 (dia_int[20], DIA[20]);

370

    buf b_dia_21 (dia_int[21], DIA[21]);

371

    buf b_dia_22 (dia_int[22], DIA[22]);

372

    buf b_dia_23 (dia_int[23], DIA[23]);

373

    buf b_dia_24 (dia_int[24], DIA[24]);

374

    buf b_dia_25 (dia_int[25], DIA[25]);

375

    buf b_dia_26 (dia_int[26], DIA[26]);

376

    buf b_dia_27 (dia_int[27], DIA[27]);

377

    buf b_dia_28 (dia_int[28], DIA[28]);

378

    buf b_dia_29 (dia_int[29], DIA[29]);

379

    buf b_dia_30 (dia_int[30], DIA[30]);

380

    buf b_dia_31 (dia_int[31], DIA[31]);

381

    buf b_dipa_0 (dipa_int[0], DIPA[0]);

382

    buf b_dipa_1 (dipa_int[1], DIPA[1]);

383

    buf b_dipa_2 (dipa_int[2], DIPA[2]);

384

    buf b_dipa_3 (dipa_int[3], DIPA[3]);

385

    buf b_ena (ena_int, ENA);

386

    buf b_clka (clka_int, CLKA);

387

    buf b_ssra (ssra_int, SSRA);

388

    buf b_wea (wea_int, WEA);

389

    buf b_addrb_0 (addrb_int[0], ADDRB[0]);

390

    buf b_addrb_1 (addrb_int[1], ADDRB[1]);

391

    buf b_addrb_2 (addrb_int[2], ADDRB[2]);

392

    buf b_addrb_3 (addrb_int[3], ADDRB[3]);

393

    buf b_addrb_4 (addrb_int[4], ADDRB[4]);

394

    buf b_addrb_5 (addrb_int[5], ADDRB[5]);

395

    buf b_addrb_6 (addrb_int[6], ADDRB[6]);

396

    buf b_addrb_7 (addrb_int[7], ADDRB[7]);

397

    buf b_addrb_8 (addrb_int[8], ADDRB[8]);

398

    buf b_dib_0 (dib_int[0], DIB[0]);

399

    buf b_dib_1 (dib_int[1], DIB[1]);

400

    buf b_dib_2 (dib_int[2], DIB[2]);

401

    buf b_dib_3 (dib_int[3], DIB[3]);

402

    buf b_dib_4 (dib_int[4], DIB[4]);

403

    buf b_dib_5 (dib_int[5], DIB[5]);

404

    buf b_dib_6 (dib_int[6], DIB[6]);

405

    buf b_dib_7 (dib_int[7], DIB[7]);

406

    buf b_dib_8 (dib_int[8], DIB[8]);

407

    buf b_dib_9 (dib_int[9], DIB[9]);

408

    buf b_dib_10 (dib_int[10], DIB[10]);

409

    buf b_dib_11 (dib_int[11], DIB[11]);

410

    buf b_dib_12 (dib_int[12], DIB[12]);

411

    buf b_dib_13 (dib_int[13], DIB[13]);

412

    buf b_dib_14 (dib_int[14], DIB[14]);

413

    buf b_dib_15 (dib_int[15], DIB[15]);

414

    buf b_dib_16 (dib_int[16], DIB[16]);

415

    buf b_dib_17 (dib_int[17], DIB[17]);

416

    buf b_dib_18 (dib_int[18], DIB[18]);

417

    buf b_dib_19 (dib_int[19], DIB[19]);

418

    buf b_dib_20 (dib_int[20], DIB[20]);

419

    buf b_dib_21 (dib_int[21], DIB[21]);

420

    buf b_dib_22 (dib_int[22], DIB[22]);

421

    buf b_dib_23 (dib_int[23], DIB[23]);

422

    buf b_dib_24 (dib_int[24], DIB[24]);

423

    buf b_dib_25 (dib_int[25], DIB[25]);

424

    buf b_dib_26 (dib_int[26], DIB[26]);

425

    buf b_dib_27 (dib_int[27], DIB[27]);

426

    buf b_dib_28 (dib_int[28], DIB[28]);

427

    buf b_dib_29 (dib_int[29], DIB[29]);

428

    buf b_dib_30 (dib_int[30], DIB[30]);

429

    buf b_dib_31 (dib_int[31], DIB[31]);

430

    buf b_dipb_0 (dipb_int[0], DIPB[0]);

431

    buf b_dipb_1 (dipb_int[1], DIPB[1]);

432

    buf b_dipb_2 (dipb_int[2], DIPB[2]);

433

    buf b_dipb_3 (dipb_int[3], DIPB[3]);

434

    buf b_enb (enb_int, ENB);

435

    buf b_clkb (clkb_int, CLKB);

436

    buf b_ssrb (ssrb_int, SSRB);

437

    buf b_web (web_int, WEB);

438

439

    initial begin

440

	for (count = 0; count < 256; count = count + 1) begin

441

	    mem[count]		  <= INIT_00[count];

442

	    mem[256 * 1 + count]  <= INIT_01[count];

443

	    mem[256 * 2 + count]  <= INIT_02[count];

444

	    mem[256 * 3 + count]  <= INIT_03[count];

445

	    mem[256 * 4 + count]  <= INIT_04[count];

446

	    mem[256 * 5 + count]  <= INIT_05[count];

447

	    mem[256 * 6 + count]  <= INIT_06[count];

448

	    mem[256 * 7 + count]  <= INIT_07[count];

449

	    mem[256 * 8 + count]  <= INIT_08[count];

450

	    mem[256 * 9 + count]  <= INIT_09[count];

451

	    mem[256 * 10 + count] <= INIT_0A[count];

452

	    mem[256 * 11 + count] <= INIT_0B[count];

453

	    mem[256 * 12 + count] <= INIT_0C[count];

454

	    mem[256 * 13 + count] <= INIT_0D[count];

455

	    mem[256 * 14 + count] <= INIT_0E[count];

456

	    mem[256 * 15 + count] <= INIT_0F[count];

457

	    mem[256 * 16 + count] <= INIT_10[count];

458

	    mem[256 * 17 + count] <= INIT_11[count];

459

	    mem[256 * 18 + count] <= INIT_12[count];

460

	    mem[256 * 19 + count] <= INIT_13[count];

461

	    mem[256 * 20 + count] <= INIT_14[count];

462

	    mem[256 * 21 + count] <= INIT_15[count];

463

	    mem[256 * 22 + count] <= INIT_16[count];

464

	    mem[256 * 23 + count] <= INIT_17[count];

465

	    mem[256 * 24 + count] <= INIT_18[count];

466

	    mem[256 * 25 + count] <= INIT_19[count];

467

	    mem[256 * 26 + count] <= INIT_1A[count];

468

	    mem[256 * 27 + count] <= INIT_1B[count];

469

	    mem[256 * 28 + count] <= INIT_1C[count];

470

	    mem[256 * 29 + count] <= INIT_1D[count];

471

	    mem[256 * 30 + count] <= INIT_1E[count];

472

	    mem[256 * 31 + count] <= INIT_1F[count];

473

	    mem[256 * 32 + count] <= INIT_20[count];

474

	    mem[256 * 33 + count] <= INIT_21[count];

475

	    mem[256 * 34 + count] <= INIT_22[count];

476

	    mem[256 * 35 + count] <= INIT_23[count];

477

	    mem[256 * 36 + count] <= INIT_24[count];

478

	    mem[256 * 37 + count] <= INIT_25[count];

479

	    mem[256 * 38 + count] <= INIT_26[count];

480

	    mem[256 * 39 + count] <= INIT_27[count];

481

	    mem[256 * 40 + count] <= INIT_28[count];

482

	    mem[256 * 41 + count] <= INIT_29[count];

483

	    mem[256 * 42 + count] <= INIT_2A[count];

484

	    mem[256 * 43 + count] <= INIT_2B[count];

485

	    mem[256 * 44 + count] <= INIT_2C[count];

486

	    mem[256 * 45 + count] <= INIT_2D[count];

487

	    mem[256 * 46 + count] <= INIT_2E[count];

488

	    mem[256 * 47 + count] <= INIT_2F[count];

489

	    mem[256 * 48 + count] <= INIT_30[count];

490

	    mem[256 * 49 + count] <= INIT_31[count];

491

	    mem[256 * 50 + count] <= INIT_32[count];

492

	    mem[256 * 51 + count] <= INIT_33[count];

493

	    mem[256 * 52 + count] <= INIT_34[count];

494

	    mem[256 * 53 + count] <= INIT_35[count];

495

	    mem[256 * 54 + count] <= INIT_36[count];

496

	    mem[256 * 55 + count] <= INIT_37[count];

497

	    mem[256 * 56 + count] <= INIT_38[count];

498

	    mem[256 * 57 + count] <= INIT_39[count];

499

	    mem[256 * 58 + count] <= INIT_3A[count];

500

	    mem[256 * 59 + count] <= INIT_3B[count];

501

	    mem[256 * 60 + count] <= INIT_3C[count];

502

	    mem[256 * 61 + count] <= INIT_3D[count];

503

	    mem[256 * 62 + count] <= INIT_3E[count];

504

	    mem[256 * 63 + count] <= INIT_3F[count];

505

	    mem[256 * 64 + count] <= INITP_00[count];

506

	    mem[256 * 65 + count] <= INITP_01[count];

507

	    mem[256 * 66 + count] <= INITP_02[count];

508

	    mem[256 * 67 + count] <= INITP_03[count];

509

	    mem[256 * 68 + count] <= INITP_04[count];

510

	    mem[256 * 69 + count] <= INITP_05[count];

511

	    mem[256 * 70 + count] <= INITP_06[count];

512

	    mem[256 * 71 + count] <= INITP_07[count];

513

end

514

	address_collision <= 0;

515

	address_collision_a_b <= 0;

516

	address_collision_b_a <= 0;

517

	change_clka <= 0;

518

	change_clkb <= 0;

519

	data_collision <= 0;

520

	data_collision_a_b <= 0;

521

	data_collision_b_a <= 0;

522

	memory_collision <= 0;

523

	memory_collision_a_b <= 0;

524

	memory_collision_b_a <= 0;

525

	setup_all_a_b <= 0;

526

	setup_all_b_a <= 0;

527

	setup_zero <= 0;

528

	setup_rf_a_b <= 0;

529

	setup_rf_b_a <= 0;

530

end

531

532

    assign data_addra_int = addra_int * 32;

533

    assign data_addra_reg = addra_reg * 32;

534

    assign data_addrb_int = addrb_int * 32;

535

    assign data_addrb_reg = addrb_reg * 32;

536

    assign parity_addra_int = 16384 + addra_int * 4;

537

    assign parity_addra_reg = 16384 + addra_reg * 4;

538

    assign parity_addrb_int = 16384 + addrb_int * 4;

539

    assign parity_addrb_reg = 16384 + addrb_reg * 4;

540

541

542

    initial begin

543

544

	display_flag = 1;

545

546

	case (SIM_COLLISION_CHECK)

547

548

	    "NONE" : begin

549

		         assign setup_all_a_b = 1'b0;

550

	                 assign setup_all_b_a = 1'b0;

551

	                 assign setup_zero = 1'b0;

552

	                 assign setup_rf_a_b = 1'b0;

553

	                 assign setup_rf_b_a = 1'b0;

554

	                 assign display_flag = 0;

555

end

556

	    "WARNING_ONLY" : begin

557

		                 assign data_collision = 2'b00;

558

	                         assign data_collision_a_b = 2'b00;

559

	                         assign data_collision_b_a = 2'b00;

560

	                         assign memory_collision = 1'b0;

561

	                         assign memory_collision_a_b = 1'b0;

562

	                         assign memory_collision_b_a = 1'b0;

563

end

564

	    "GENERATE_X_ONLY" : begin

565

		                    assign display_flag = 0;

566

end

567

	    "ALL" : ;

568

	    default : begin

569

		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);

570

		          $finish;

571

end

572

573

	endcase // case(SIM_COLLISION_CHECK)

574

575

    end // initial begin

576

577

578

    always @(posedge clka_int) begin

579

	time_clka = $time;

580

	#0 time_clkb_clka = time_clka - time_clkb;

581

	change_clka = ~change_clka;

582

end

583

584

    always @(posedge clkb_int) begin

585

	time_clkb = $time;

586

	#0 time_clka_clkb = time_clkb - time_clka;

587

	change_clkb = ~change_clkb;

588

end

589

590

    always @(change_clkb) begin

591

	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))

592

	    setup_all_a_b = 1;

593

	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))

594

	    setup_rf_a_b = 1;

595

end

596

597

    always @(change_clka) begin

598

	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))

599

	    setup_all_b_a = 1;

600

	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))

601

	    setup_rf_b_a = 1;

602

end

603

604

    always @(change_clkb or change_clka) begin

605

	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))

606

	    setup_zero = 1;

607

end

608

609

    always @(posedge setup_zero) begin

610

	if ((ena_int == 1) && (wea_int == 1) &&

611

	    (enb_int == 1) && (web_int == 1) &&

612

	    (data_addra_int[14:5] == data_addrb_int[14:5]))

613

	    memory_collision <= 1;

614

end

615

616

    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin

617

	if ((ena_reg == 1) && (wea_reg == 1) &&

618

	    (enb_int == 1) && (web_int == 1) &&

619

	    (data_addra_reg[14:5] == data_addrb_int[14:5]))

620

	    memory_collision_a_b <= 1;

621

end

622

623

    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin

624

	if ((ena_int == 1) && (wea_int == 1) &&

625

	    (enb_reg == 1) && (web_reg == 1) &&

626

	    (data_addra_int[14:5] == data_addrb_reg[14:5]))

627

	    memory_collision_b_a <= 1;

628

end

629

630

    always @(posedge setup_all_a_b) begin

631

	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin

632

	if ((ena_reg == 1) && (enb_int == 1)) begin

633

	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})

634

		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

635

		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

636

		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end

637

//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

638

//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

639

//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

640

		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end

641

		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end

642

		6'b101011 : begin display_wa_wb; end

643

		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

644

//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

645

		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

646

		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

647

//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

648

		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

649

		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

650

//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

651

		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

652

		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

653

		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

654

		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

655

//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

656

//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

657

//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

658

		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

659

		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

660

		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

661

	    endcase

662

end

663

end

664

	setup_all_a_b <= 0;

665

end

666

667

668

    always @(posedge setup_all_b_a) begin

669

	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin

670

	if ((ena_int == 1) && (enb_reg == 1)) begin

671

	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})

672

		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

673

//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

674

		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end

675

		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

676

//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

677

		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end

678

		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

679

		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

680

		6'b101011 : begin display_wa_wb; end

681

		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

682

		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

683

		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

684

		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

685

		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

686

		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

687

		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

688

		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

689

		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

690

		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

691

		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

692

		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

693

//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

694

//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

695

//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

696

		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

697

		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

698

		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

699

	    endcase

700

end

701

end

702

	setup_all_b_a <= 0;

703

end

704

705

706

    always @(posedge setup_zero) begin

707

	if (data_addra_int[14:5] == data_addrb_int[14:5]) begin

708

	if ((ena_int == 1) && (enb_int == 1)) begin

709

	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})

710

		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end

711

		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end

712

		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end

713

		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end

714

		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end

715

		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end

716

		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end

717

		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end

718

		6'b101011 : begin display_wa_wb; end

719

		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end

720

//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end

721

		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end

722

		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end

723

//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end

724

		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end

725

		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end

726

//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end

727

		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end

728

		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end

729

		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end

730

		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end

731

//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end

732

//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end

733

//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end

734

		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end

735

		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end

736

		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end

737

	    endcase

738

end

739

end

740

	setup_zero <= 0;

741

end

742

743

    task display_ra_wb;

744

    begin

745

	if (display_flag)

746

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);

747

end

748

    endtask

749

750

    task display_wa_rb;

751

    begin

752

	if (display_flag)

753

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);

754

end

755

    endtask

756

757

    task display_wa_wb;

758

    begin

759

	if (display_flag)

760

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);

761

end

762

    endtask

763

764

765

    always @(posedge setup_rf_a_b) begin

766

	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin

767

	if ((ena_reg == 1) && (enb_int == 1)) begin

768

	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})

769

//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

770

//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

771

//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

772

		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

773

		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

774

		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end

775

//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

776

//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

777

//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

778

//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

779

//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

780

//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

781

//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

782

//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

783

//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

784

//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

785

//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

786

//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

787

//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

788

//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

789

//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

790

		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

791

		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

792

		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

793

//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

794

//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

795

//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

796

	    endcase

797

end

798

end

799

	setup_rf_a_b <= 0;

800

end

801

802

803

    always @(posedge setup_rf_b_a) begin

804

	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin

805

	if ((ena_int == 1) && (enb_reg == 1)) begin

806

	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})

807

//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

808

		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

809

//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

810

//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

811

		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

812

//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

813

//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

814

		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

815

//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

816

//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

817

		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

818

//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

819

//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

820

		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

821

//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

822

//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

823

		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

824

//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

825

//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

826

//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

827

//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

828

//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

829

//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

830

//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

831

//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

832

//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

833

//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

834

	    endcase

835

end

836

end

837

	setup_rf_b_a <= 0;

838

end

839

840

841

    always @(posedge clka_int) begin

842

	addra_reg <= addra_int;

843

	ena_reg <= ena_int;

844

	ssra_reg <= ssra_int;

845

	wea_reg <= wea_int;

846

end

847

848

    always @(posedge clkb_int) begin

849

	addrb_reg <= addrb_int;

850

	enb_reg <= enb_int;

851

	ssrb_reg <= ssrb_int;

852

	web_reg <= web_int;

853

end

854

855

    // Data

856

    always @(posedge memory_collision) begin

857

	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin

858

	    mem[data_addra_int + dmi] <= 1'bX;

859

end

860

	memory_collision <= 0;

861

end

862

863

    always @(posedge memory_collision_a_b) begin

864

	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin

865

	    mem[data_addra_reg + dmi] <= 1'bX;

866

end

867

	memory_collision_a_b <= 0;

868

end

869

870

    always @(posedge memory_collision_b_a) begin

871

	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin

872

	    mem[data_addra_int + dmi] <= 1'bX;

873

end

874

	memory_collision_b_a <= 0;

875

end

876

877

    always @(posedge data_collision[1]) begin

878

	if (ssra_int == 0) begin

879

	    doa_out <= 32'bX;

880

end

881

	data_collision[1] <= 0;

882

end

883

884

    always @(posedge data_collision[0]) begin

885

	if (ssrb_int == 0) begin

886

	    dob_out <= 32'bX;

887

end

888

	data_collision[0] <= 0;

889

end

890

891

    always @(posedge data_collision_a_b[1]) begin

892

	if (ssra_reg == 0) begin

893

	    doa_out <= 32'bX;

894

end

895

	data_collision_a_b[1] <= 0;

896

end

897

898

    always @(posedge data_collision_a_b[0]) begin

899

	if (ssrb_int == 0) begin

900

	    dob_out <= 32'bX;

901

end

902

	data_collision_a_b[0] <= 0;

903

end

904

905

    always @(posedge data_collision_b_a[1]) begin

906

	if (ssra_int == 0) begin

907

	    doa_out <= 32'bX;

908

end

909

	data_collision_b_a[1] <= 0;

910

end

911

912

    always @(posedge data_collision_b_a[0]) begin

913

	if (ssrb_reg == 0) begin

914

	dob_out <= 32'bX;

915

end

916

	data_collision_b_a[0] <= 0;

917

end

918

919

920

    // Parity

921

    always @(posedge memory_collision) begin

922

	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin

923

	    mem[parity_addra_int + pmi] <= 1'bX;

924

end

925

end

926

927

    always @(posedge memory_collision_a_b) begin

928

	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin

929

	    mem[parity_addra_reg + pmi] <= 1'bX;

930

end

931

end

932

933

    always @(posedge memory_collision_b_a) begin

934

	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin

935

	    mem[parity_addra_int + pmi] <= 1'bX;

936

end

937

end

938

939

    always @(posedge data_collision[1]) begin

940

	if (ssra_int == 0) begin

941

	    dopa_out <= 4'bX;

942

end

943

end

944

945

    always @(posedge data_collision[0]) begin

946

	if (ssrb_int == 0) begin

947

	    dopb_out <= 4'bX;

948

end

949

end

950

951

    always @(posedge data_collision_a_b[1]) begin

952

	if (ssra_reg == 0) begin

953

	    dopa_out <= 4'bX;

954

end

955

end

956

957

    always @(posedge data_collision_a_b[0]) begin

958

	if (ssrb_int == 0) begin

959

	dopb_out <= 4'bX;

960

end

961

end

962

963

    always @(posedge data_collision_b_a[1]) begin

964

	if (ssra_int == 0) begin

965

	    dopa_out <= 4'bX;

966

end

967

end

968

969

    always @(posedge data_collision_b_a[0]) begin

970

	if (ssrb_reg == 0) begin

971

	    dopb_out <= 4'bX;

972

end

973

end

974

975

976

    initial begin

977

	case (WRITE_MODE_A)

978

	    "WRITE_FIRST" : wr_mode_a <= 2'b00;

979

	    "READ_FIRST"  : wr_mode_a <= 2'b01;

980

	    "NO_CHANGE"   : wr_mode_a <= 2'b10;

981

	    default       : begin

982

				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);

983

				$finish;

984

end

985

	endcase

986

end

987

988

    initial begin

989

	case (WRITE_MODE_B)

990

	    "WRITE_FIRST" : wr_mode_b <= 2'b00;

991

	    "READ_FIRST"  : wr_mode_b <= 2'b01;

992

	    "NO_CHANGE"   : wr_mode_b <= 2'b10;

993

	    default       : begin

994

				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);

995

				$finish;

996

end

997

	endcase

998

end

999

1000

    // Port A

1001

    always @(posedge clka_int) begin

1002

	if (ena_int == 1'b1) begin

1003

	    if (ssra_int == 1'b1) begin

1004

		doa_out[0] <= SRVAL_A[0];

1005

		doa_out[1] <= SRVAL_A[1];

1006

		doa_out[2] <= SRVAL_A[2];

1007

		doa_out[3] <= SRVAL_A[3];

1008

		doa_out[4] <= SRVAL_A[4];

1009

		doa_out[5] <= SRVAL_A[5];

1010

		doa_out[6] <= SRVAL_A[6];

1011

		doa_out[7] <= SRVAL_A[7];

1012

		doa_out[8] <= SRVAL_A[8];

1013

		doa_out[9] <= SRVAL_A[9];

1014

		doa_out[10] <= SRVAL_A[10];

1015

		doa_out[11] <= SRVAL_A[11];

1016

		doa_out[12] <= SRVAL_A[12];

1017

		doa_out[13] <= SRVAL_A[13];

1018

		doa_out[14] <= SRVAL_A[14];

1019

		doa_out[15] <= SRVAL_A[15];

1020

		doa_out[16] <= SRVAL_A[16];

1021

		doa_out[17] <= SRVAL_A[17];

1022

		doa_out[18] <= SRVAL_A[18];

1023

		doa_out[19] <= SRVAL_A[19];

1024

		doa_out[20] <= SRVAL_A[20];

1025

		doa_out[21] <= SRVAL_A[21];

1026

		doa_out[22] <= SRVAL_A[22];

1027

		doa_out[23] <= SRVAL_A[23];

1028

		doa_out[24] <= SRVAL_A[24];

1029

		doa_out[25] <= SRVAL_A[25];

1030

		doa_out[26] <= SRVAL_A[26];

1031

		doa_out[27] <= SRVAL_A[27];

1032

		doa_out[28] <= SRVAL_A[28];

1033

		doa_out[29] <= SRVAL_A[29];

1034

		doa_out[30] <= SRVAL_A[30];

1035

		doa_out[31] <= SRVAL_A[31];

1036

		dopa_out[0] <= SRVAL_A[32];

1037

		dopa_out[1] <= SRVAL_A[33];

1038

		dopa_out[2] <= SRVAL_A[34];

1039

		dopa_out[3] <= SRVAL_A[35];

1040

end

1041

	    else begin

1042

		if (wea_int == 1'b1) begin

1043

		    if (wr_mode_a == 2'b00) begin

1044

			doa_out <= dia_int;

1045

			dopa_out <= dipa_int;

1046

end

1047

		    else if (wr_mode_a == 2'b01) begin

1048

			doa_out[0] <= mem[data_addra_int + 0];

1049

			doa_out[1] <= mem[data_addra_int + 1];

1050

			doa_out[2] <= mem[data_addra_int + 2];

1051

			doa_out[3] <= mem[data_addra_int + 3];

1052

			doa_out[4] <= mem[data_addra_int + 4];

1053

			doa_out[5] <= mem[data_addra_int + 5];

1054

			doa_out[6] <= mem[data_addra_int + 6];

1055

			doa_out[7] <= mem[data_addra_int + 7];

1056

			doa_out[8] <= mem[data_addra_int + 8];

1057

			doa_out[9] <= mem[data_addra_int + 9];

1058

			doa_out[10] <= mem[data_addra_int + 10];

1059

			doa_out[11] <= mem[data_addra_int + 11];

1060

			doa_out[12] <= mem[data_addra_int + 12];

1061

			doa_out[13] <= mem[data_addra_int + 13];

1062

			doa_out[14] <= mem[data_addra_int + 14];

1063

			doa_out[15] <= mem[data_addra_int + 15];

1064

			doa_out[16] <= mem[data_addra_int + 16];

1065

			doa_out[17] <= mem[data_addra_int + 17];

1066

			doa_out[18] <= mem[data_addra_int + 18];

1067

			doa_out[19] <= mem[data_addra_int + 19];

1068

			doa_out[20] <= mem[data_addra_int + 20];

1069

			doa_out[21] <= mem[data_addra_int + 21];

1070

			doa_out[22] <= mem[data_addra_int + 22];

1071

			doa_out[23] <= mem[data_addra_int + 23];

1072

			doa_out[24] <= mem[data_addra_int + 24];

1073

			doa_out[25] <= mem[data_addra_int + 25];

1074

			doa_out[26] <= mem[data_addra_int + 26];

1075

			doa_out[27] <= mem[data_addra_int + 27];

1076

			doa_out[28] <= mem[data_addra_int + 28];

1077

			doa_out[29] <= mem[data_addra_int + 29];

1078

			doa_out[30] <= mem[data_addra_int + 30];

1079

			doa_out[31] <= mem[data_addra_int + 31];

1080

			dopa_out[0] <= mem[parity_addra_int + 0];

1081

			dopa_out[1] <= mem[parity_addra_int + 1];

1082

			dopa_out[2] <= mem[parity_addra_int + 2];

1083

			dopa_out[3] <= mem[parity_addra_int + 3];

1084

end

1085

end

1086

		else begin

1087

		    doa_out[0] <= mem[data_addra_int + 0];

1088

		    doa_out[1] <= mem[data_addra_int + 1];

1089

		    doa_out[2] <= mem[data_addra_int + 2];

1090

		    doa_out[3] <= mem[data_addra_int + 3];

1091

		    doa_out[4] <= mem[data_addra_int + 4];

1092

		    doa_out[5] <= mem[data_addra_int + 5];

1093

		    doa_out[6] <= mem[data_addra_int + 6];

1094

		    doa_out[7] <= mem[data_addra_int + 7];

1095

		    doa_out[8] <= mem[data_addra_int + 8];

1096

		    doa_out[9] <= mem[data_addra_int + 9];

1097

		    doa_out[10] <= mem[data_addra_int + 10];

1098

		    doa_out[11] <= mem[data_addra_int + 11];

1099

		    doa_out[12] <= mem[data_addra_int + 12];

1100

		    doa_out[13] <= mem[data_addra_int + 13];

1101

		    doa_out[14] <= mem[data_addra_int + 14];

1102

		    doa_out[15] <= mem[data_addra_int + 15];

1103

		    doa_out[16] <= mem[data_addra_int + 16];

1104

		    doa_out[17] <= mem[data_addra_int + 17];

1105

		    doa_out[18] <= mem[data_addra_int + 18];

1106

		    doa_out[19] <= mem[data_addra_int + 19];

1107

		    doa_out[20] <= mem[data_addra_int + 20];

1108

		    doa_out[21] <= mem[data_addra_int + 21];

1109

		    doa_out[22] <= mem[data_addra_int + 22];

1110

		    doa_out[23] <= mem[data_addra_int + 23];

1111

		    doa_out[24] <= mem[data_addra_int + 24];

1112

		    doa_out[25] <= mem[data_addra_int + 25];

1113

		    doa_out[26] <= mem[data_addra_int + 26];

1114

		    doa_out[27] <= mem[data_addra_int + 27];

1115

		    doa_out[28] <= mem[data_addra_int + 28];

1116

		    doa_out[29] <= mem[data_addra_int + 29];

1117

		    doa_out[30] <= mem[data_addra_int + 30];

1118

		    doa_out[31] <= mem[data_addra_int + 31];

1119

		    dopa_out[0] <= mem[parity_addra_int + 0];

1120

		    dopa_out[1] <= mem[parity_addra_int + 1];

1121

		    dopa_out[2] <= mem[parity_addra_int + 2];

1122

		    dopa_out[3] <= mem[parity_addra_int + 3];

1123

end

1124

end

1125

end

1126

end

1127

1128

    always @(posedge clka_int) begin

1129

	if (ena_int == 1'b1 && wea_int == 1'b1) begin

1130

	    mem[data_addra_int + 0] <= dia_int[0];

1131

	    mem[data_addra_int + 1] <= dia_int[1];

1132

	    mem[data_addra_int + 2] <= dia_int[2];

1133

	    mem[data_addra_int + 3] <= dia_int[3];

1134

	    mem[data_addra_int + 4] <= dia_int[4];

1135

	    mem[data_addra_int + 5] <= dia_int[5];

1136

	    mem[data_addra_int + 6] <= dia_int[6];

1137

	    mem[data_addra_int + 7] <= dia_int[7];

1138

	    mem[data_addra_int + 8] <= dia_int[8];

1139

	    mem[data_addra_int + 9] <= dia_int[9];

1140

	    mem[data_addra_int + 10] <= dia_int[10];

1141

	    mem[data_addra_int + 11] <= dia_int[11];

1142

	    mem[data_addra_int + 12] <= dia_int[12];

1143

	    mem[data_addra_int + 13] <= dia_int[13];

1144

	    mem[data_addra_int + 14] <= dia_int[14];

1145

	    mem[data_addra_int + 15] <= dia_int[15];

1146

	    mem[data_addra_int + 16] <= dia_int[16];

1147

	    mem[data_addra_int + 17] <= dia_int[17];

1148

	    mem[data_addra_int + 18] <= dia_int[18];

1149

	    mem[data_addra_int + 19] <= dia_int[19];

1150

	    mem[data_addra_int + 20] <= dia_int[20];

1151

	    mem[data_addra_int + 21] <= dia_int[21];

1152

	    mem[data_addra_int + 22] <= dia_int[22];

1153

	    mem[data_addra_int + 23] <= dia_int[23];

1154

	    mem[data_addra_int + 24] <= dia_int[24];

1155

	    mem[data_addra_int + 25] <= dia_int[25];

1156

	    mem[data_addra_int + 26] <= dia_int[26];

1157

	    mem[data_addra_int + 27] <= dia_int[27];

1158

	    mem[data_addra_int + 28] <= dia_int[28];

1159

	    mem[data_addra_int + 29] <= dia_int[29];

1160

	    mem[data_addra_int + 30] <= dia_int[30];

1161

	    mem[data_addra_int + 31] <= dia_int[31];

1162

	    mem[parity_addra_int + 0] <= dipa_int[0];

1163

	    mem[parity_addra_int + 1] <= dipa_int[1];

1164

	    mem[parity_addra_int + 2] <= dipa_int[2];

1165

	    mem[parity_addra_int + 3] <= dipa_int[3];

1166

end

1167

end

1168

1169

    // Port B

1170

    always @(posedge clkb_int) begin

1171

	if (enb_int == 1'b1) begin

1172

	    if (ssrb_int == 1'b1) begin

1173

		dob_out[0] <= SRVAL_B[0];

1174

		dob_out[1] <= SRVAL_B[1];

1175

		dob_out[2] <= SRVAL_B[2];

1176

		dob_out[3] <= SRVAL_B[3];

1177

		dob_out[4] <= SRVAL_B[4];

1178

		dob_out[5] <= SRVAL_B[5];

1179

		dob_out[6] <= SRVAL_B[6];

1180

		dob_out[7] <= SRVAL_B[7];

1181

		dob_out[8] <= SRVAL_B[8];

1182

		dob_out[9] <= SRVAL_B[9];

1183

		dob_out[10] <= SRVAL_B[10];

1184

		dob_out[11] <= SRVAL_B[11];

1185

		dob_out[12] <= SRVAL_B[12];

1186

		dob_out[13] <= SRVAL_B[13];

1187

		dob_out[14] <= SRVAL_B[14];

1188

		dob_out[15] <= SRVAL_B[15];

1189

		dob_out[16] <= SRVAL_B[16];

1190

		dob_out[17] <= SRVAL_B[17];

1191

		dob_out[18] <= SRVAL_B[18];

1192

		dob_out[19] <= SRVAL_B[19];

1193

		dob_out[20] <= SRVAL_B[20];

1194

		dob_out[21] <= SRVAL_B[21];

1195

		dob_out[22] <= SRVAL_B[22];

1196

		dob_out[23] <= SRVAL_B[23];

1197

		dob_out[24] <= SRVAL_B[24];

1198

		dob_out[25] <= SRVAL_B[25];

1199

		dob_out[26] <= SRVAL_B[26];

1200

		dob_out[27] <= SRVAL_B[27];

1201

		dob_out[28] <= SRVAL_B[28];

1202

		dob_out[29] <= SRVAL_B[29];

1203

		dob_out[30] <= SRVAL_B[30];

1204

		dob_out[31] <= SRVAL_B[31];

1205

		dopb_out[0] <= SRVAL_B[32];

1206

		dopb_out[1] <= SRVAL_B[33];

1207

		dopb_out[2] <= SRVAL_B[34];

1208

		dopb_out[3] <= SRVAL_B[35];

1209

end

1210

	    else begin

1211

		if (web_int == 1'b1) begin

1212

		    if (wr_mode_b == 2'b00) begin

1213

			dob_out <= dib_int;

1214

			dopb_out <= dipb_int;

1215

end

1216

		    else if (wr_mode_b == 2'b01) begin

1217

			dob_out[0] <= mem[data_addrb_int + 0];

1218

			dob_out[1] <= mem[data_addrb_int + 1];

1219

			dob_out[2] <= mem[data_addrb_int + 2];

1220

			dob_out[3] <= mem[data_addrb_int + 3];

1221

			dob_out[4] <= mem[data_addrb_int + 4];

1222

			dob_out[5] <= mem[data_addrb_int + 5];

1223

			dob_out[6] <= mem[data_addrb_int + 6];

1224

			dob_out[7] <= mem[data_addrb_int + 7];

1225

			dob_out[8] <= mem[data_addrb_int + 8];

1226

			dob_out[9] <= mem[data_addrb_int + 9];

1227

			dob_out[10] <= mem[data_addrb_int + 10];

1228

			dob_out[11] <= mem[data_addrb_int + 11];

1229

			dob_out[12] <= mem[data_addrb_int + 12];

1230

			dob_out[13] <= mem[data_addrb_int + 13];

1231

			dob_out[14] <= mem[data_addrb_int + 14];

1232

			dob_out[15] <= mem[data_addrb_int + 15];

1233

			dob_out[16] <= mem[data_addrb_int + 16];

1234

			dob_out[17] <= mem[data_addrb_int + 17];

1235

			dob_out[18] <= mem[data_addrb_int + 18];

1236

			dob_out[19] <= mem[data_addrb_int + 19];

1237

			dob_out[20] <= mem[data_addrb_int + 20];

1238

			dob_out[21] <= mem[data_addrb_int + 21];

1239

			dob_out[22] <= mem[data_addrb_int + 22];

1240

			dob_out[23] <= mem[data_addrb_int + 23];

1241

			dob_out[24] <= mem[data_addrb_int + 24];

1242

			dob_out[25] <= mem[data_addrb_int + 25];

1243

			dob_out[26] <= mem[data_addrb_int + 26];

1244

			dob_out[27] <= mem[data_addrb_int + 27];

1245

			dob_out[28] <= mem[data_addrb_int + 28];

1246

			dob_out[29] <= mem[data_addrb_int + 29];

1247

			dob_out[30] <= mem[data_addrb_int + 30];

1248

			dob_out[31] <= mem[data_addrb_int + 31];

1249

			dopb_out[0] <= mem[parity_addrb_int + 0];

1250

			dopb_out[1] <= mem[parity_addrb_int + 1];

1251

			dopb_out[2] <= mem[parity_addrb_int + 2];

1252

			dopb_out[3] <= mem[parity_addrb_int + 3];

1253

end

1254

end

1255

		else begin

1256

		    dob_out[0] <= mem[data_addrb_int + 0];

1257

		    dob_out[1] <= mem[data_addrb_int + 1];

1258

		    dob_out[2] <= mem[data_addrb_int + 2];

1259

		    dob_out[3] <= mem[data_addrb_int + 3];

1260

		    dob_out[4] <= mem[data_addrb_int + 4];

1261

		    dob_out[5] <= mem[data_addrb_int + 5];

1262

		    dob_out[6] <= mem[data_addrb_int + 6];

1263

		    dob_out[7] <= mem[data_addrb_int + 7];

1264

		    dob_out[8] <= mem[data_addrb_int + 8];

1265

		    dob_out[9] <= mem[data_addrb_int + 9];

1266

		    dob_out[10] <= mem[data_addrb_int + 10];

1267

		    dob_out[11] <= mem[data_addrb_int + 11];

1268

		    dob_out[12] <= mem[data_addrb_int + 12];

1269

		    dob_out[13] <= mem[data_addrb_int + 13];

1270

		    dob_out[14] <= mem[data_addrb_int + 14];

1271

		    dob_out[15] <= mem[data_addrb_int + 15];

1272

		    dob_out[16] <= mem[data_addrb_int + 16];

1273

		    dob_out[17] <= mem[data_addrb_int + 17];

1274

		    dob_out[18] <= mem[data_addrb_int + 18];

1275

		    dob_out[19] <= mem[data_addrb_int + 19];

1276

		    dob_out[20] <= mem[data_addrb_int + 20];

1277

		    dob_out[21] <= mem[data_addrb_int + 21];

1278

		    dob_out[22] <= mem[data_addrb_int + 22];

1279

		    dob_out[23] <= mem[data_addrb_int + 23];

1280

		    dob_out[24] <= mem[data_addrb_int + 24];

1281

		    dob_out[25] <= mem[data_addrb_int + 25];

1282

		    dob_out[26] <= mem[data_addrb_int + 26];

1283

		    dob_out[27] <= mem[data_addrb_int + 27];

1284

		    dob_out[28] <= mem[data_addrb_int + 28];

1285

		    dob_out[29] <= mem[data_addrb_int + 29];

1286

		    dob_out[30] <= mem[data_addrb_int + 30];

1287

		    dob_out[31] <= mem[data_addrb_int + 31];

1288

		    dopb_out[0] <= mem[parity_addrb_int + 0];

1289

		    dopb_out[1] <= mem[parity_addrb_int + 1];

1290

		    dopb_out[2] <= mem[parity_addrb_int + 2];

1291

		    dopb_out[3] <= mem[parity_addrb_int + 3];

1292

end

1293

end

1294

end

1295

end

1296

1297

    always @(posedge clkb_int) begin

1298

	if (enb_int == 1'b1 && web_int == 1'b1) begin

1299

	    mem[data_addrb_int + 0] <= dib_int[0];

1300

	    mem[data_addrb_int + 1] <= dib_int[1];

1301

	    mem[data_addrb_int + 2] <= dib_int[2];

1302

	    mem[data_addrb_int + 3] <= dib_int[3];

1303

	    mem[data_addrb_int + 4] <= dib_int[4];

1304

	    mem[data_addrb_int + 5] <= dib_int[5];

1305

	    mem[data_addrb_int + 6] <= dib_int[6];

1306

	    mem[data_addrb_int + 7] <= dib_int[7];

1307

	    mem[data_addrb_int + 8] <= dib_int[8];

1308

	    mem[data_addrb_int + 9] <= dib_int[9];

1309

	    mem[data_addrb_int + 10] <= dib_int[10];

1310

	    mem[data_addrb_int + 11] <= dib_int[11];

1311

	    mem[data_addrb_int + 12] <= dib_int[12];

1312

	    mem[data_addrb_int + 13] <= dib_int[13];

1313

	    mem[data_addrb_int + 14] <= dib_int[14];

1314

	    mem[data_addrb_int + 15] <= dib_int[15];

1315

	    mem[data_addrb_int + 16] <= dib_int[16];

1316

	    mem[data_addrb_int + 17] <= dib_int[17];

1317

	    mem[data_addrb_int + 18] <= dib_int[18];

1318

	    mem[data_addrb_int + 19] <= dib_int[19];

1319

	    mem[data_addrb_int + 20] <= dib_int[20];

1320

	    mem[data_addrb_int + 21] <= dib_int[21];

1321

	    mem[data_addrb_int + 22] <= dib_int[22];

1322

	    mem[data_addrb_int + 23] <= dib_int[23];

1323

	    mem[data_addrb_int + 24] <= dib_int[24];

1324

	    mem[data_addrb_int + 25] <= dib_int[25];

1325

	    mem[data_addrb_int + 26] <= dib_int[26];

1326

	    mem[data_addrb_int + 27] <= dib_int[27];

1327

	    mem[data_addrb_int + 28] <= dib_int[28];

1328

	    mem[data_addrb_int + 29] <= dib_int[29];

1329

	    mem[data_addrb_int + 30] <= dib_int[30];

1330

	    mem[data_addrb_int + 31] <= dib_int[31];

1331

	    mem[parity_addrb_int + 0] <= dipb_int[0];

1332

	    mem[parity_addrb_int + 1] <= dipb_int[1];

1333

	    mem[parity_addrb_int + 2] <= dipb_int[2];

1334

	    mem[parity_addrb_int + 3] <= dipb_int[3];

1335

end

1336

end

1337

1338

    specify

1339

	(CLKA *> DOA) = (100, 100);

1340

	(CLKA *> DOPA) = (100, 100);

1341

	(CLKB *> DOB) = (100, 100);

1342

	(CLKB *> DOPB) = (100, 100);

1343

    endspecify

1344

1345

endmodule

1346

1347

`else

1348

1349

// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $

1350

///////////////////////////////////////////////////////////////////////////////

1351

// Copyright (c) 1995/2005 Xilinx, Inc.

1352

// All Right Reserved.

1353

///////////////////////////////////////////////////////////////////////////////

1354

//   ____  ____

1355

//  /   /\/   /

1356

// /___/  \  /    Vendor : Xilinx

1357

// \   \   \/     Version : 10.1

1358

//  \   \         Description : Xilinx Timing Simulation Library Component

1359

//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM

1360

// /___/   /\     Filename : RAMB16_S36_S36.v

1361

// \   \  /  \    Timestamp : Thu Mar 10 16:44:01 PST 2005

1362

//  \___\/\___\

1363

//

1364

// Revision:

1365

//    03/23/04 - Initial version.

1366

//    03/10/05 - Initialized outputs.

1367

//    02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).

1368

// End Revision

1369

1370

`timescale 1 ps/1 ps

1371

1372

module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);

1373

1374

    parameter INIT_A = 36'h0;

1375

    parameter INIT_B = 36'h0;

1376

    parameter SRVAL_A = 36'h0;

1377

    parameter SRVAL_B = 36'h0;

1378

    parameter WRITE_MODE_A = "WRITE_FIRST";

1379

    parameter WRITE_MODE_B = "WRITE_FIRST";

1380

    parameter SIM_COLLISION_CHECK = "ALL";

1381

    localparam SETUP_ALL = 1000;

1382

    localparam SETUP_READ_FIRST = 3000;

1383

1384

    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1385

    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1386

    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1387

    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1388

    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1389

    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1390

    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1391

    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1392

    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1393

    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1394

    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1395

    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1396

    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1397

    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1398

    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1399

    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1400

    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1401

    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1402

    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1403

    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1404

    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1405

    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1406

    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1407

    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1408

    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1409

    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1410

    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1411

    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1412

    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1413

    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1414

    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1415

    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1416

    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1417

    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1418

    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1419

    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1420

    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1421

    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1422

    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1423

    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1424

    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1425

    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1426

    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1427

    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1428

    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1429

    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1430

    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1431

    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1432

    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1433

    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1434

    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1435

    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1436

    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1437

    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1438

    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1439

    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1440

    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1441

    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1442

    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1443

    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1444

    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1445

    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1446

    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1447

    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1448

    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1449

    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1450

    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1451

    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1452

    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1453

    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1454

    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1455

    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;

1456

1457

    output [31:0] DOA;

1458

    output [3:0] DOPA;

1459

    output [31:0] DOB;

1460

    output [3:0] DOPB;

1461

1462

    input [8:0] ADDRA;

1463

    input [31:0] DIA;

1464

    input [3:0] DIPA;

1465

    input ENA, CLKA, WEA, SSRA;

1466

    input [8:0] ADDRB;

1467

    input [31:0] DIB;

1468

    input [3:0] DIPB;

1469

    input ENB, CLKB, WEB, SSRB;

1470

1471

    reg [31:0] doa_out = INIT_A[31:0];

1472

    reg [3:0] dopa_out = INIT_A[35:32];

1473

    reg [31:0] dob_out = INIT_B[31:0];

1474

    reg [3:0] dopb_out = INIT_B[35:32];

1475

1476

    reg [31:0] mem [511:0];

1477

    reg [3:0] memp [511:0];

1478

1479

    reg [8:0] count, countp;

1480

    reg [1:0] wr_mode_a, wr_mode_b;

1481

1482

    reg [5:0] dmi, dbi;

1483

    reg [5:0] pmi, pbi;

1484

1485

    wire [8:0] addra_int;

1486

    reg [8:0] addra_reg;

1487

    wire [31:0] dia_int;

1488

    wire [3:0] dipa_int;

1489

    wire ena_int, clka_int, wea_int, ssra_int;

1490

    reg ena_reg, wea_reg, ssra_reg;

1491

    wire [8:0] addrb_int;

1492

    reg [8:0] addrb_reg;

1493

    wire [31:0] dib_int;

1494

    wire [3:0] dipb_int;

1495

    wire enb_int, clkb_int, web_int, ssrb_int;

1496

    reg display_flag, output_flag;

1497

    reg enb_reg, web_reg, ssrb_reg;

1498

1499

    time time_clka, time_clkb;

1500

    time time_clka_clkb;

1501

    time time_clkb_clka;

1502

1503

    reg setup_all_a_b;

1504

    reg setup_all_b_a;

1505

    reg setup_zero;

1506

    reg setup_rf_a_b;

1507

    reg setup_rf_b_a;

1508

    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;

1509

    reg memory_collision, memory_collision_a_b, memory_collision_b_a;

1510

    reg change_clka;

1511

    reg change_clkb;

1512

1513

    wire [14:0] data_addra_int;

1514

    wire [14:0] data_addra_reg;

1515

    wire [14:0] data_addrb_int;

1516

    wire [14:0] data_addrb_reg;

1517

1518

    wire dia_enable = ena_int && wea_int;

1519

    wire dib_enable = enb_int && web_int;

1520

1521

    tri0 GSR = glbl.GSR;

1522

    wire gsr_int;

1523

1524

    buf b_gsr (gsr_int, GSR);

1525

1526

    buf b_doa [31:0] (DOA, doa_out);

1527

    buf b_dopa [3:0] (DOPA, dopa_out);

1528

    buf b_addra [8:0] (addra_int, ADDRA);

1529

    buf b_dia [31:0] (dia_int, DIA);

1530

    buf b_dipa [3:0] (dipa_int, DIPA);

1531

    buf b_ena (ena_int, ENA);

1532

    buf b_clka (clka_int, CLKA);

1533

    buf b_ssra (ssra_int, SSRA);

1534

    buf b_wea (wea_int, WEA);

1535

1536

    buf b_dob [31:0] (DOB, dob_out);

1537

    buf b_dopb [3:0] (DOPB, dopb_out);

1538

    buf b_addrb [8:0] (addrb_int, ADDRB);

1539

    buf b_dib [31:0] (dib_int, DIB);

1540

    buf b_dipb [3:0] (dipb_int, DIPB);

1541

    buf b_enb (enb_int, ENB);

1542

    buf b_clkb (clkb_int, CLKB);

1543

    buf b_ssrb (ssrb_int, SSRB);

1544

    buf b_web (web_int, WEB);

1545

1546

1547

    always @(gsr_int)

1548

	if (gsr_int) begin

1549

	    assign {dopa_out, doa_out} = INIT_A;

1550

	    assign {dopb_out, dob_out} = INIT_B;

1551

end

1552

	else begin

1553

	    deassign doa_out;

1554

	    deassign dopa_out;

1555

	    deassign dob_out;

1556

	    deassign dopb_out;

1557

end

1558

1559

1560

    initial begin

1561

1562

	for (count = 0; count < 8; count = count + 1) begin

1563

	    mem[count]          = INIT_00[(count * 32) +: 32];

1564

	    mem[8 * 1 + count]  = INIT_01[(count * 32) +: 32];

1565

	    mem[8 * 2 + count]  = INIT_02[(count * 32) +: 32];

1566

	    mem[8 * 3 + count]  = INIT_03[(count * 32) +: 32];

1567

	    mem[8 * 4 + count]  = INIT_04[(count * 32) +: 32];

1568

	    mem[8 * 5 + count]  = INIT_05[(count * 32) +: 32];

1569

	    mem[8 * 6 + count]  = INIT_06[(count * 32) +: 32];

1570

	    mem[8 * 7 + count]  = INIT_07[(count * 32) +: 32];

1571

	    mem[8 * 8 + count]  = INIT_08[(count * 32) +: 32];

1572

	    mem[8 * 9 + count]  = INIT_09[(count * 32) +: 32];

1573

	    mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32];

1574

	    mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32];

1575

	    mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32];

1576

	    mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32];

1577

	    mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32];

1578

	    mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32];

1579

	    mem[8 * 16 + count] = INIT_10[(count * 32) +: 32];

1580

	    mem[8 * 17 + count] = INIT_11[(count * 32) +: 32];

1581

	    mem[8 * 18 + count] = INIT_12[(count * 32) +: 32];

1582

	    mem[8 * 19 + count] = INIT_13[(count * 32) +: 32];

1583

	    mem[8 * 20 + count] = INIT_14[(count * 32) +: 32];

1584

	    mem[8 * 21 + count] = INIT_15[(count * 32) +: 32];

1585

	    mem[8 * 22 + count] = INIT_16[(count * 32) +: 32];

1586

	    mem[8 * 23 + count] = INIT_17[(count * 32) +: 32];

1587

	    mem[8 * 24 + count] = INIT_18[(count * 32) +: 32];

1588

	    mem[8 * 25 + count] = INIT_19[(count * 32) +: 32];

1589

	    mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32];

1590

	    mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32];

1591

	    mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32];

1592

	    mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32];

1593

	    mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32];

1594

	    mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32];

1595

	    mem[8 * 32 + count] = INIT_20[(count * 32) +: 32];

1596

	    mem[8 * 33 + count] = INIT_21[(count * 32) +: 32];

1597

	    mem[8 * 34 + count] = INIT_22[(count * 32) +: 32];

1598

	    mem[8 * 35 + count] = INIT_23[(count * 32) +: 32];

1599

	    mem[8 * 36 + count] = INIT_24[(count * 32) +: 32];

1600

	    mem[8 * 37 + count] = INIT_25[(count * 32) +: 32];

1601

	    mem[8 * 38 + count] = INIT_26[(count * 32) +: 32];

1602

	    mem[8 * 39 + count] = INIT_27[(count * 32) +: 32];

1603

	    mem[8 * 40 + count] = INIT_28[(count * 32) +: 32];

1604

	    mem[8 * 41 + count] = INIT_29[(count * 32) +: 32];

1605

	    mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32];

1606

	    mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32];

1607

	    mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32];

1608

	    mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32];

1609

	    mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32];

1610

	    mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32];

1611

	    mem[8 * 48 + count] = INIT_30[(count * 32) +: 32];

1612

	    mem[8 * 49 + count] = INIT_31[(count * 32) +: 32];

1613

	    mem[8 * 50 + count] = INIT_32[(count * 32) +: 32];

1614

	    mem[8 * 51 + count] = INIT_33[(count * 32) +: 32];

1615

	    mem[8 * 52 + count] = INIT_34[(count * 32) +: 32];

1616

	    mem[8 * 53 + count] = INIT_35[(count * 32) +: 32];

1617

	    mem[8 * 54 + count] = INIT_36[(count * 32) +: 32];

1618

	    mem[8 * 55 + count] = INIT_37[(count * 32) +: 32];

1619

	    mem[8 * 56 + count] = INIT_38[(count * 32) +: 32];

1620

	    mem[8 * 57 + count] = INIT_39[(count * 32) +: 32];

1621

	    mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32];

1622

	    mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32];

1623

	    mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32];

1624

	    mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32];

1625

	    mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32];

1626

	    mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32];

1627

end

1628

1629

// initiate parity start

1630

	for (countp = 0; countp < 64; countp = countp + 1) begin

1631

	    memp[countp]          = INITP_00[(countp * 4) +: 4];

1632

	    memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4];

1633

	    memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4];

1634

	    memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4];

1635

	    memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4];

1636

	    memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4];

1637

	    memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4];

1638

	    memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4];

1639

end

1640

// initiate parity end

1641

1642

	change_clka <= 0;

1643

	change_clkb <= 0;

1644

	data_collision <= 0;

1645

	data_collision_a_b <= 0;

1646

	data_collision_b_a <= 0;

1647

	memory_collision <= 0;

1648

	memory_collision_a_b <= 0;

1649

	memory_collision_b_a <= 0;

1650

	setup_all_a_b <= 0;

1651

	setup_all_b_a <= 0;

1652

	setup_zero <= 0;

1653

	setup_rf_a_b <= 0;

1654

	setup_rf_b_a <= 0;

1655

end

1656

1657

    assign data_addra_int = addra_int * 32;

1658

    assign data_addra_reg = addra_reg * 32;

1659

    assign data_addrb_int = addrb_int * 32;

1660

    assign data_addrb_reg = addrb_reg * 32;

1661

1662

1663

    initial begin

1664

1665

	display_flag = 1;

1666

	output_flag = 1;

1667

1668

	case (SIM_COLLISION_CHECK)

1669

1670

	    "NONE" : begin

1671

		         output_flag = 0;

1672

	                 display_flag = 0;

1673

end

1674

	    "WARNING_ONLY" : output_flag = 0;

1675

	    "GENERATE_X_ONLY" : display_flag = 0;

1676

	    "ALL" : ;

1677

1678

	    default : begin

1679

		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);

1680

		          $finish;

1681

end

1682

1683

	endcase // case(SIM_COLLISION_CHECK)

1684

1685

    end // initial begin

1686

1687

1688

    always @(posedge clka_int) begin

1689

	if ((output_flag || display_flag)) begin

1690

	    time_clka = $time;

1691

	    #0 time_clkb_clka = time_clka - time_clkb;

1692

	    change_clka = ~change_clka;

1693

end

1694

end

1695

1696

    always @(posedge clkb_int) begin

1697

	if ((output_flag || display_flag)) begin

1698

	    time_clkb = $time;

1699

	    #0 time_clka_clkb = time_clkb - time_clka;

1700

	    change_clkb = ~change_clkb;

1701

end

1702

end

1703

1704

    always @(change_clkb) begin

1705

	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))

1706

	    setup_all_a_b = 1;

1707

	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))

1708

	    setup_rf_a_b = 1;

1709

end

1710

1711

    always @(change_clka) begin

1712

	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))

1713

	    setup_all_b_a = 1;

1714

	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))

1715

	    setup_rf_b_a = 1;

1716

end

1717

1718

    always @(change_clkb or change_clka) begin

1719

	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))

1720

	    setup_zero = 1;

1721

end

1722

1723

    always @(posedge setup_zero) begin

1724

	if ((ena_int == 1) && (wea_int == 1) &&

1725

	    (enb_int == 1) && (web_int == 1) &&

1726

	    (data_addra_int[14:5] == data_addrb_int[14:5]))

1727

	    memory_collision <= 1;

1728

end

1729

1730

    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin

1731

	if ((ena_reg == 1) && (wea_reg == 1) &&

1732

	    (enb_int == 1) && (web_int == 1) &&

1733

	    (data_addra_reg[14:5] == data_addrb_int[14:5]))

1734

	    memory_collision_a_b <= 1;

1735

end

1736

1737

    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin

1738

	if ((ena_int == 1) && (wea_int == 1) &&

1739

	    (enb_reg == 1) && (web_reg == 1) &&

1740

	    (data_addra_int[14:5] == data_addrb_reg[14:5]))

1741

	    memory_collision_b_a <= 1;

1742

end

1743

1744

    always @(posedge setup_all_a_b) begin

1745

	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin

1746

	if ((ena_reg == 1) && (enb_int == 1)) begin

1747

	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})

1748

		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

1749

		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

1750

		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end

1751

//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1752

//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1753

//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1754

		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end

1755

		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end

1756

		6'b101011 : begin display_wa_wb; end

1757

		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1758

//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1759

		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1760

		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1761

//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1762

		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1763

		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1764

//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1765

		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end

1766

		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1767

		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1768

		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1769

//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1770

//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1771

//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1772

		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1773

		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1774

		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1775

	    endcase

1776

end

1777

end

1778

	setup_all_a_b <= 0;

1779

end

1780

1781

1782

    always @(posedge setup_all_b_a) begin

1783

	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin

1784

	if ((ena_int == 1) && (enb_reg == 1)) begin

1785

	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})

1786

		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

1787

//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1788

		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end

1789

		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

1790

//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1791

		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end

1792

		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

1793

		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

1794

		6'b101011 : begin display_wa_wb; end

1795

		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1796

		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1797

		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1798

		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1799

		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1800

		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1801

		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1802

		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1803

		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1804

		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1805

		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1806

		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1807

//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1808

//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1809

//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1810

		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1811

		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1812

		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end

1813

	    endcase

1814

end

1815

end

1816

	setup_all_b_a <= 0;

1817

end

1818

1819

1820

    always @(posedge setup_zero) begin

1821

	if (data_addra_int[14:5] == data_addrb_int[14:5]) begin

1822

	if ((ena_int == 1) && (enb_int == 1)) begin

1823

	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})

1824

		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end

1825

		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end

1826

		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end

1827

		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end

1828

		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end

1829

		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end

1830

		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end

1831

		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end

1832

		6'b101011 : begin display_wa_wb; end

1833

		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end

1834

//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end

1835

		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end

1836

		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end

1837

//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end

1838

		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end

1839

		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end

1840

//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end

1841

		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end

1842

		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end

1843

		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end

1844

		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end

1845

//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end

1846

//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end

1847

//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end

1848

		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end

1849

		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end

1850

		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end

1851

	    endcase

1852

end

1853

end

1854

	setup_zero <= 0;

1855

end

1856

1857

    task display_ra_wb;

1858

    begin

1859

	if (display_flag)

1860

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);

1861

end

1862

    endtask

1863

1864

    task display_wa_rb;

1865

    begin

1866

	if (display_flag)

1867

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);

1868

end

1869

    endtask

1870

1871

    task display_wa_wb;

1872

    begin

1873

	if (display_flag)

1874

        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);

1875

end

1876

    endtask

1877

1878

1879

    always @(posedge setup_rf_a_b) begin

1880

	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin

1881

	if ((ena_reg == 1) && (enb_int == 1)) begin

1882

	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})

1883

//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1884

//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1885

//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1886

		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

1887

		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end

1888

		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end

1889

//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1890

//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1891

//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end

1892

//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1893

//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1894

//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1895

//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1896

//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1897

//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1898

//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1899

//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1900

//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end

1901

//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1902

//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1903

//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1904

		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1905

		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1906

		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end

1907

//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1908

//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1909

//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end

1910

	    endcase

1911

end

1912

end

1913

	setup_rf_a_b <= 0;

1914

end

1915

1916

1917

    always @(posedge setup_rf_b_a) begin

1918

	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin

1919

	if ((ena_int == 1) && (enb_reg == 1)) begin

1920

	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})

1921

//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1922

		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

1923

//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1924

//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1925

		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end

1926

//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1927

//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1928

		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end

1929

//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end

1930

//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1931

		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1932

//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1933

//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1934

		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1935

//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1936

//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1937

		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end

1938

//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end

1939

//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1940

//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1941

//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1942

//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1943

//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1944

//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1945

//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1946

//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1947

//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end

1948

	    endcase

1949

end

1950

end

1951

	setup_rf_b_a <= 0;

1952

end

1953

1954

1955

    always @(posedge clka_int) begin

1956

	if ((output_flag || display_flag)) begin

1957

	    addra_reg <= addra_int;

1958

	    ena_reg <= ena_int;

1959

	    ssra_reg <= ssra_int;

1960

	    wea_reg <= wea_int;

1961

end

1962

end

1963

1964

    always @(posedge clkb_int) begin

1965

	if ((output_flag || display_flag)) begin

1966

	    addrb_reg <= addrb_int;

1967

	    enb_reg <= enb_int;

1968

	    ssrb_reg <= ssrb_int;

1969

	    web_reg <= web_int;

1970

end

1971

end

1972

1973

1974

    // Data

1975

    always @(posedge memory_collision) begin

1976

	if ((output_flag || display_flag)) begin

1977

	    mem[addra_int] <= 32'bx;

1978

	    memory_collision <= 0;

1979

end

1980

1981

end

1982

1983

    always @(posedge memory_collision_a_b) begin

1984

	if ((output_flag || display_flag)) begin

1985

	    mem[addra_reg] <= 32'bx;

1986

	    memory_collision_a_b <= 0;

1987

end

1988

end

1989

1990

    always @(posedge memory_collision_b_a) begin

1991

	if ((output_flag || display_flag)) begin

1992

	    mem[addra_int] <= 32'bx;

1993

	    memory_collision_b_a <= 0;

1994

end

1995

end

1996

1997

    always @(posedge data_collision[1]) begin

1998

	if (ssra_int == 0 && output_flag) begin

1999

	    doa_out <= #100 32'bX;

2000

end

2001

	data_collision[1] <= 0;

2002

end

2003

2004

    always @(posedge data_collision[0]) begin

2005

	if (ssrb_int == 0 && output_flag) begin

2006

	    dob_out <= #100 32'bX;

2007

end

2008

	data_collision[0] <= 0;

2009

end

2010

2011

    always @(posedge data_collision_a_b[1]) begin

2012

	if (ssra_reg == 0 && output_flag) begin

2013

	    doa_out <= #100 32'bX;

2014

end

2015

	data_collision_a_b[1] <= 0;

2016

end

2017

2018

    always @(posedge data_collision_a_b[0]) begin

2019

	if (ssrb_int == 0 && output_flag) begin

2020

	    dob_out <= #100 32'bX;

2021

end

2022

	data_collision_a_b[0] <= 0;

2023

end

2024

2025

    always @(posedge data_collision_b_a[1]) begin

2026

	if (ssra_int == 0 && output_flag) begin

2027

	    doa_out <= #100 32'bX;

2028

end

2029

	data_collision_b_a[1] <= 0;

2030

end

2031

2032

    always @(posedge data_collision_b_a[0]) begin

2033

	if (ssrb_reg == 0 && output_flag) begin

2034

	    dob_out <= #100 32'bX;

2035

end

2036

	data_collision_b_a[0] <= 0;

2037

end

2038

2039

// x parity start

2040

    always @(posedge memory_collision) begin

2041

	if ((output_flag || display_flag))

2042

	    memp[addra_int] <= 4'bx;

2043

end

2044

2045

    always @(posedge memory_collision_a_b) begin

2046

	if ((output_flag || display_flag))

2047

	    memp[addra_reg] <= 4'bx;

2048

end

2049

2050

    always @(posedge memory_collision_b_a) begin

2051

	if ((output_flag || display_flag))

2052

	    memp[addra_int] <= 4'bx;

2053

end

2054

2055

    always @(posedge data_collision[1]) begin

2056

	if (ssra_int == 0 && output_flag) begin

2057

	    dopa_out <= #100 4'bX;

2058

end

2059

end

2060

2061

    always @(posedge data_collision_a_b[1]) begin

2062

	if (ssra_reg == 0 && output_flag) begin

2063

	    dopa_out <= #100 4'bX;

2064

end

2065

end

2066

2067

2068

    always @(posedge data_collision_b_a[1]) begin

2069

	if (ssra_int == 0 && output_flag) begin

2070

	    dopa_out <= #100 4'bX;

2071

end

2072

end

2073

2074

    always @(posedge data_collision[0]) begin

2075

	if (ssrb_int == 0 && output_flag) begin

2076

	    dopb_out <= #100 4'bx;

2077

end

2078

end

2079

2080

    always @(posedge data_collision_a_b[0]) begin

2081

	if (ssrb_int == 0 && output_flag) begin

2082

	    dopb_out <= #100 4'bx;

2083

end

2084

end

2085

2086

    always @(posedge data_collision_b_a[0]) begin

2087

	if (ssrb_reg == 0 && output_flag) begin

2088

	    dopb_out <= #100 4'bx;

2089

end

2090

end

2091

// x parity end

2092

2093

    initial begin

2094

	case (WRITE_MODE_A)

2095

	    "WRITE_FIRST" : wr_mode_a <= 2'b00;

2096

	    "READ_FIRST"  : wr_mode_a <= 2'b01;

2097

	    "NO_CHANGE"   : wr_mode_a <= 2'b10;

2098

	    default       : begin

2099

				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);

2100

				$finish;

2101

end

2102

	endcase

2103

end

2104

2105

    initial begin

2106

	case (WRITE_MODE_B)

2107

	    "WRITE_FIRST" : wr_mode_b <= 2'b00;

2108

	    "READ_FIRST"  : wr_mode_b <= 2'b01;

2109

	    "NO_CHANGE"   : wr_mode_b <= 2'b10;

2110

	    default       : begin

2111

				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);

2112

				$finish;

2113

end

2114

	endcase

2115

end

2116

2117

2118

    // Port A

2119

    always @(posedge clka_int) begin

2120

2121

	if (ena_int == 1'b1) begin

2122

2123

	    if (ssra_int == 1'b1) begin

2124

		{dopa_out, doa_out} <= #100 SRVAL_A;

2125

end

2126

	    else begin

2127

		if (wea_int == 1'b1) begin

2128

		    if (wr_mode_a == 2'b00) begin

2129

			doa_out <= #100 dia_int;

2130

			dopa_out <= #100 dipa_int;

2131

end

2132

		    else if (wr_mode_a == 2'b01) begin

2133

2134

			doa_out <= #100 mem[addra_int];

2135

			dopa_out <= #100 memp[addra_int];

2136

2137

end

2138

end

2139

		else begin

2140

2141

		    doa_out <= #100 mem[addra_int];

2142

		    dopa_out <= #100 memp[addra_int];

2143

2144

end

2145

end

2146

2147

	    // memory

2148

	    if (wea_int == 1'b1) begin

2149

		mem[addra_int] <= dia_int;

2150

		memp[addra_int] <= dipa_int;

2151

end

2152

2153

end

2154

end

2155

2156

2157

    // Port B

2158

    always @(posedge clkb_int) begin

2159

2160

	if (enb_int == 1'b1) begin

2161

2162

	    if (ssrb_int == 1'b1) begin

2163

		{dopb_out, dob_out} <= #100 SRVAL_B;

2164

end

2165

	    else begin

2166

		if (web_int == 1'b1) begin

2167

		    if (wr_mode_b == 2'b00) begin

2168

			dob_out <= #100 dib_int;

2169

			dopb_out <= #100 dipb_int;

2170

end

2171

		    else if (wr_mode_b == 2'b01) begin

2172

			dob_out <= #100 mem[addrb_int];

2173

			dopb_out <= #100 memp[addrb_int];

2174

end

2175

end

2176

		else begin

2177

		    dob_out <= #100 mem[addrb_int];

2178

		    dopb_out <= #100 memp[addrb_int];

2179

end

2180

end

2181

2182

	    // memory

2183

	    if (web_int == 1'b1) begin

2184

		mem[addrb_int] <= dib_int;

2185

		memp[addrb_int] <= dipb_int;

2186

end

2187

2188

end

2189

end

2190

2191

2192

endmodule

2193

2194

`endif

uhd

root / usrp2 / models / RAMB16_S36_S36.v @ d8aae182