Revision c9569736 host/lib/usrp/usrp1/dboard_iface.cpp
| b/host/lib/usrp/usrp1/dboard_iface.cpp | ||
|---|---|---|
| 19 | 19 |
#include "usrp1_impl.hpp" |
| 20 | 20 |
#include "fpga_regs_common.h" |
| 21 | 21 |
#include "usrp_spi_defs.h" |
| 22 |
#include "fpga_regs_standard.h" |
|
| 22 | 23 |
#include "clock_ctrl.hpp" |
| 23 | 24 |
#include "codec_ctrl.hpp" |
| 24 | 25 |
#include <uhd/usrp/dboard_iface.hpp> |
| ... | ... | |
| 37 | 38 |
usrp1_dboard_iface(usrp1_iface::sptr iface, |
| 38 | 39 |
usrp1_clock_ctrl::sptr clock, |
| 39 | 40 |
usrp1_codec_ctrl::sptr codec, |
| 40 |
usrp1_impl::dboard_slot_t dboard_slot |
|
| 41 |
){
|
|
| 41 |
usrp1_impl::dboard_slot_t dboard_slot, |
|
| 42 |
const dboard_id_t &rx_dboard_id |
|
| 43 |
): |
|
| 44 |
_dboard_slot(dboard_slot), |
|
| 45 |
_rx_dboard_id(rx_dboard_id) |
|
| 46 |
{
|
|
| 42 | 47 |
_iface = iface; |
| 43 | 48 |
_clock = clock; |
| 44 | 49 |
_codec = codec; |
| 45 |
_dboard_slot = dboard_slot; |
|
| 46 | 50 |
|
| 47 | 51 |
//init the clock rate shadows |
| 48 | 52 |
this->set_clock_rate(UNIT_RX, _clock->get_master_clock_freq()); |
| ... | ... | |
| 95 | 99 |
usrp1_clock_ctrl::sptr _clock; |
| 96 | 100 |
usrp1_codec_ctrl::sptr _codec; |
| 97 | 101 |
uhd::dict<unit_t, double> _clock_rates; |
| 98 |
usrp1_impl::dboard_slot_t _dboard_slot; |
|
| 102 |
const usrp1_impl::dboard_slot_t _dboard_slot; |
|
| 103 |
const dboard_id_t &_rx_dboard_id; |
|
| 99 | 104 |
}; |
| 100 | 105 |
|
| 101 | 106 |
/*********************************************************************** |
| ... | ... | |
| 104 | 109 |
dboard_iface::sptr usrp1_impl::make_dboard_iface(usrp1_iface::sptr iface, |
| 105 | 110 |
usrp1_clock_ctrl::sptr clock, |
| 106 | 111 |
usrp1_codec_ctrl::sptr codec, |
| 107 |
dboard_slot_t dboard_slot |
|
| 112 |
dboard_slot_t dboard_slot, |
|
| 113 |
const dboard_id_t &rx_dboard_id |
|
| 108 | 114 |
){
|
| 109 |
return dboard_iface::sptr(new usrp1_dboard_iface(iface, clock, codec, dboard_slot)); |
|
| 115 |
return dboard_iface::sptr(new usrp1_dboard_iface( |
|
| 116 |
iface, clock, codec, dboard_slot, rx_dboard_id |
|
| 117 |
)); |
|
| 110 | 118 |
} |
| 111 | 119 |
|
| 112 | 120 |
/*********************************************************************** |
| 113 | 121 |
* Clock Rates |
| 114 | 122 |
**********************************************************************/ |
| 123 |
static const dboard_id_t dbsrx_classic_id(0x0002); |
|
| 124 |
|
|
| 125 |
/* |
|
| 126 |
* Daughterboard reference clock register |
|
| 127 |
* |
|
| 128 |
* Bit 7 - 1 turns on refclk, 0 allows IO use |
|
| 129 |
* Bits 6:0 - Divider value |
|
| 130 |
*/ |
|
| 115 | 131 |
void usrp1_dboard_iface::set_clock_rate(unit_t unit, double rate) |
| 116 | 132 |
{
|
| 133 |
assert_has(this->get_clock_rates(unit), rate, "dboard clock rate"); |
|
| 117 | 134 |
_clock_rates[unit] = rate; |
| 118 |
switch(unit) {
|
|
| 119 |
case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); |
|
| 120 |
case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); |
|
| 135 |
|
|
| 136 |
if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){
|
|
| 137 |
size_t divider = size_t(rate/_clock->get_master_clock_freq()); |
|
| 138 |
switch(_dboard_slot){
|
|
| 139 |
case usrp1_impl::DBOARD_SLOT_A: |
|
| 140 |
_iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); |
|
| 141 |
break; |
|
| 142 |
|
|
| 143 |
case usrp1_impl::DBOARD_SLOT_B: |
|
| 144 |
_iface->poke32(FR_RX_B_REFCLK, (divider & 0x7f) | 0x80); |
|
| 145 |
break; |
|
| 146 |
} |
|
| 121 | 147 |
} |
| 122 | 148 |
} |
| 123 | 149 |
|
| 124 |
/* |
|
| 125 |
* TODO: if this is a dbsrx return the rate of 4MHZ and set FPGA magic |
|
| 126 |
*/ |
|
| 127 | 150 |
std::vector<double> usrp1_dboard_iface::get_clock_rates(unit_t unit) |
| 128 | 151 |
{
|
| 129 |
switch(unit) {
|
|
| 130 |
case UNIT_RX: return _clock->get_rx_dboard_clock_rates();
|
|
| 131 |
case UNIT_TX: return _clock->get_tx_dboard_clock_rates();
|
|
| 132 |
default: UHD_THROW_INVALID_CODE_PATH();
|
|
| 152 |
std::vector<double> rates;
|
|
| 153 |
if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){
|
|
| 154 |
for (size_t div = 1; div <= 127; div++)
|
|
| 155 |
rates.push_back(_clock->get_master_clock_freq() / div);
|
|
| 133 | 156 |
} |
| 157 |
else{
|
|
| 158 |
rates.push_back(_clock->get_master_clock_freq()); |
|
| 159 |
} |
|
| 160 |
return rates; |
|
| 134 | 161 |
} |
| 135 | 162 |
|
| 136 | 163 |
double usrp1_dboard_iface::get_clock_rate(unit_t unit) |
| ... | ... | |
| 138 | 165 |
return _clock_rates[unit]; |
| 139 | 166 |
} |
| 140 | 167 |
|
| 141 |
void usrp1_dboard_iface::set_clock_enabled(unit_t unit, bool enb)
|
|
| 168 |
void usrp1_dboard_iface::set_clock_enabled(unit_t, bool)
|
|
| 142 | 169 |
{
|
| 143 |
switch(unit) {
|
|
| 144 |
case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); |
|
| 145 |
case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); |
|
| 146 |
} |
|
| 170 |
//TODO we can only enable for special case anyway... |
|
| 147 | 171 |
} |
| 148 | 172 |
|
| 149 | 173 |
/*********************************************************************** |
| ... | ... | |
| 241 | 265 |
_iface->poke32(FR_ATR_RXVAL_1, value); |
| 242 | 266 |
else if (_dboard_slot == usrp1_impl::DBOARD_SLOT_B) |
| 243 | 267 |
_iface->poke32(FR_ATR_RXVAL_3, value); |
| 244 |
break;
|
|
| 268 |
break; |
|
| 245 | 269 |
case UNIT_TX: |
| 246 | 270 |
if (_dboard_slot == usrp1_impl::DBOARD_SLOT_A) |
| 247 | 271 |
_iface->poke32(FR_ATR_TXVAL_0, value); |
| ... | ... | |
| 265 | 289 |
switch(unit) {
|
| 266 | 290 |
case dboard_iface::UNIT_TX: |
| 267 | 291 |
if (slot == usrp1_impl::DBOARD_SLOT_A) |
| 268 |
return SPI_ENABLE_TX_A;
|
|
| 292 |
return SPI_ENABLE_TX_A; |
|
| 269 | 293 |
else if (slot == usrp1_impl::DBOARD_SLOT_B) |
| 270 | 294 |
return SPI_ENABLE_TX_B; |
| 271 | 295 |
else |
| 272 | 296 |
break; |
| 273 | 297 |
case dboard_iface::UNIT_RX: |
| 274 | 298 |
if (slot == usrp1_impl::DBOARD_SLOT_A) |
| 275 |
return SPI_ENABLE_RX_A;
|
|
| 299 |
return SPI_ENABLE_RX_A; |
|
| 276 | 300 |
else if (slot == usrp1_impl::DBOARD_SLOT_B) |
| 277 | 301 |
return SPI_ENABLE_RX_B; |
| 278 | 302 |
else |
Also available in: Unified diff