Revision c9569736
| b/host/lib/usrp/usrp1/clock_ctrl.cpp | ||
|---|---|---|
| 46 | 46 |
return master_clock_rate; |
| 47 | 47 |
} |
| 48 | 48 |
|
| 49 |
/*********************************************************************** |
|
| 50 |
* RX Dboard Clock Control (output 9, divider 3) |
|
| 51 |
**********************************************************************/ |
|
| 52 |
void enable_rx_dboard_clock(bool) |
|
| 53 |
{
|
|
| 54 |
std::cerr << "USRP: enable_rx_dboard_clock() disabled" << std::endl; |
|
| 55 |
_iface->poke32(FR_RX_A_REFCLK, 0); |
|
| 56 |
_iface->poke32(FR_RX_B_REFCLK, 0); |
|
| 57 |
} |
|
| 58 |
|
|
| 59 |
std::vector<double> get_rx_dboard_clock_rates(void) |
|
| 60 |
{
|
|
| 61 |
#if 0 |
|
| 62 |
std::vector<double> rates; |
|
| 63 |
for (size_t div = 1; div <= 127; div++) |
|
| 64 |
rates.push_back(master_clock_rate / div); |
|
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return rates; |
|
| 66 |
#else |
|
| 67 |
return std::vector<double>(1, master_clock_rate); |
|
| 68 |
#endif |
|
| 69 |
} |
|
| 70 |
|
|
| 71 |
/* |
|
| 72 |
* Daughterboard reference clock register |
|
| 73 |
* |
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* Bit 7 - 1 turns on refclk, 0 allows IO use |
|
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* Bits 6:0 - Divider value |
|
| 76 |
*/ |
|
| 77 |
void set_rx_dboard_clock_rate(double) |
|
| 78 |
{
|
|
| 79 |
#if 0 |
|
| 80 |
assert_has(get_rx_dboard_clock_rates(), rate, "rx dboard clock rate"); |
|
| 81 |
size_t divider = size_t(rate/master_clock_rate); |
|
| 82 |
_iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); |
|
| 83 |
#else |
|
| 84 |
std::cerr << "USRP: set_rx_dboard_clock_rate() disabled" << std::endl; |
|
| 85 |
_iface->poke32(FR_RX_A_REFCLK, 0); |
|
| 86 |
_iface->poke32(FR_RX_B_REFCLK, 0); |
|
| 87 |
#endif |
|
| 88 |
} |
|
| 89 |
|
|
| 90 |
/*********************************************************************** |
|
| 91 |
* TX Dboard Clock Control |
|
| 92 |
**********************************************************************/ |
|
| 93 |
void enable_tx_dboard_clock(bool) |
|
| 94 |
{
|
|
| 95 |
std::cerr << "USRP: set_tx_dboard_clock() disabled" << std::endl; |
|
| 96 |
_iface->poke32(FR_TX_A_REFCLK, 0); |
|
| 97 |
_iface->poke32(FR_TX_B_REFCLK, 0); |
|
| 98 |
|
|
| 99 |
} |
|
| 100 |
|
|
| 101 |
std::vector<double> get_tx_dboard_clock_rates(void) |
|
| 102 |
{
|
|
| 103 |
return get_rx_dboard_clock_rates(); //same master clock, same dividers... |
|
| 104 |
} |
|
| 105 |
|
|
| 106 |
void set_tx_dboard_clock_rate(double) |
|
| 107 |
{
|
|
| 108 |
std::cerr << "USRP: set_tx_dboard_clock_rate() disabled" << std::endl; |
|
| 109 |
_iface->poke32(FR_TX_A_REFCLK, 0); |
|
| 110 |
_iface->poke32(FR_TX_B_REFCLK, 0); |
|
| 111 |
} |
|
| 112 |
|
|
| 113 | 49 |
private: |
| 114 | 50 |
usrp1_iface::sptr _iface; |
| 115 | 51 |
|
| b/host/lib/usrp/usrp1/clock_ctrl.hpp | ||
|---|---|---|
| 45 | 45 |
*/ |
| 46 | 46 |
virtual double get_master_clock_freq(void) = 0; |
| 47 | 47 |
|
| 48 |
/*! |
|
| 49 |
* Get the possible rates of the rx dboard clock. |
|
| 50 |
* \return a vector of clock rates in Hz |
|
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*/ |
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virtual std::vector<double> get_rx_dboard_clock_rates(void) = 0; |
|
| 53 |
|
|
| 54 |
/*! |
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* Get the possible rates of the tx dboard clock. |
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* \return a vector of clock rates in Hz |
|
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*/ |
|
| 58 |
virtual std::vector<double> get_tx_dboard_clock_rates(void) = 0; |
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|
|
| 60 |
/*! |
|
| 61 |
* Set the rx dboard clock rate to a possible rate. |
|
| 62 |
* \param rate the new clock rate in Hz |
|
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* \throw exception when rate cannot be achieved |
|
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*/ |
|
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virtual void set_rx_dboard_clock_rate(double rate) = 0; |
|
| 66 |
|
|
| 67 |
/*! |
|
| 68 |
* Set the tx dboard clock rate to a possible rate. |
|
| 69 |
* \param rate the new clock rate in Hz |
|
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* \throw exception when rate cannot be achieved |
|
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*/ |
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virtual void set_tx_dboard_clock_rate(double rate) = 0; |
|
| 73 |
|
|
| 74 |
/*! |
|
| 75 |
* Enable/disable the rx dboard clock. |
|
| 76 |
* \param enb true to enable |
|
| 77 |
*/ |
|
| 78 |
virtual void enable_rx_dboard_clock(bool enb) = 0; |
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| 79 |
|
|
| 80 |
/*! |
|
| 81 |
* Enable/disable the tx dboard clock. |
|
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* \param enb true to enable |
|
| 83 |
*/ |
|
| 84 |
virtual void enable_tx_dboard_clock(bool enb) = 0; |
|
| 85 |
|
|
| 86 | 48 |
}; |
| 87 | 49 |
|
| 88 | 50 |
#endif /* INCLUDED_USRP1_CLOCK_CTRL_HPP */ |
| b/host/lib/usrp/usrp1/dboard_iface.cpp | ||
|---|---|---|
| 19 | 19 |
#include "usrp1_impl.hpp" |
| 20 | 20 |
#include "fpga_regs_common.h" |
| 21 | 21 |
#include "usrp_spi_defs.h" |
| 22 |
#include "fpga_regs_standard.h" |
|
| 22 | 23 |
#include "clock_ctrl.hpp" |
| 23 | 24 |
#include "codec_ctrl.hpp" |
| 24 | 25 |
#include <uhd/usrp/dboard_iface.hpp> |
| ... | ... | |
| 37 | 38 |
usrp1_dboard_iface(usrp1_iface::sptr iface, |
| 38 | 39 |
usrp1_clock_ctrl::sptr clock, |
| 39 | 40 |
usrp1_codec_ctrl::sptr codec, |
| 40 |
usrp1_impl::dboard_slot_t dboard_slot |
|
| 41 |
){
|
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usrp1_impl::dboard_slot_t dboard_slot, |
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const dboard_id_t &rx_dboard_id |
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): |
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_dboard_slot(dboard_slot), |
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_rx_dboard_id(rx_dboard_id) |
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{
|
|
| 42 | 47 |
_iface = iface; |
| 43 | 48 |
_clock = clock; |
| 44 | 49 |
_codec = codec; |
| 45 |
_dboard_slot = dboard_slot; |
|
| 46 | 50 |
|
| 47 | 51 |
//init the clock rate shadows |
| 48 | 52 |
this->set_clock_rate(UNIT_RX, _clock->get_master_clock_freq()); |
| ... | ... | |
| 95 | 99 |
usrp1_clock_ctrl::sptr _clock; |
| 96 | 100 |
usrp1_codec_ctrl::sptr _codec; |
| 97 | 101 |
uhd::dict<unit_t, double> _clock_rates; |
| 98 |
usrp1_impl::dboard_slot_t _dboard_slot; |
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const usrp1_impl::dboard_slot_t _dboard_slot; |
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const dboard_id_t &_rx_dboard_id; |
|
| 99 | 104 |
}; |
| 100 | 105 |
|
| 101 | 106 |
/*********************************************************************** |
| ... | ... | |
| 104 | 109 |
dboard_iface::sptr usrp1_impl::make_dboard_iface(usrp1_iface::sptr iface, |
| 105 | 110 |
usrp1_clock_ctrl::sptr clock, |
| 106 | 111 |
usrp1_codec_ctrl::sptr codec, |
| 107 |
dboard_slot_t dboard_slot |
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dboard_slot_t dboard_slot, |
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const dboard_id_t &rx_dboard_id |
|
| 108 | 114 |
){
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return dboard_iface::sptr(new usrp1_dboard_iface(iface, clock, codec, dboard_slot)); |
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return dboard_iface::sptr(new usrp1_dboard_iface( |
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iface, clock, codec, dboard_slot, rx_dboard_id |
|
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)); |
|
| 110 | 118 |
} |
| 111 | 119 |
|
| 112 | 120 |
/*********************************************************************** |
| 113 | 121 |
* Clock Rates |
| 114 | 122 |
**********************************************************************/ |
| 123 |
static const dboard_id_t dbsrx_classic_id(0x0002); |
|
| 124 |
|
|
| 125 |
/* |
|
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* Daughterboard reference clock register |
|
| 127 |
* |
|
| 128 |
* Bit 7 - 1 turns on refclk, 0 allows IO use |
|
| 129 |
* Bits 6:0 - Divider value |
|
| 130 |
*/ |
|
| 115 | 131 |
void usrp1_dboard_iface::set_clock_rate(unit_t unit, double rate) |
| 116 | 132 |
{
|
| 133 |
assert_has(this->get_clock_rates(unit), rate, "dboard clock rate"); |
|
| 117 | 134 |
_clock_rates[unit] = rate; |
| 118 |
switch(unit) {
|
|
| 119 |
case UNIT_RX: return _clock->set_rx_dboard_clock_rate(rate); |
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| 120 |
case UNIT_TX: return _clock->set_tx_dboard_clock_rate(rate); |
|
| 135 |
|
|
| 136 |
if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){
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|
| 137 |
size_t divider = size_t(rate/_clock->get_master_clock_freq()); |
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switch(_dboard_slot){
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| 139 |
case usrp1_impl::DBOARD_SLOT_A: |
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_iface->poke32(FR_RX_A_REFCLK, (divider & 0x7f) | 0x80); |
|
| 141 |
break; |
|
| 142 |
|
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| 143 |
case usrp1_impl::DBOARD_SLOT_B: |
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_iface->poke32(FR_RX_B_REFCLK, (divider & 0x7f) | 0x80); |
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break; |
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| 146 |
} |
|
| 121 | 147 |
} |
| 122 | 148 |
} |
| 123 | 149 |
|
| 124 |
/* |
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* TODO: if this is a dbsrx return the rate of 4MHZ and set FPGA magic |
|
| 126 |
*/ |
|
| 127 | 150 |
std::vector<double> usrp1_dboard_iface::get_clock_rates(unit_t unit) |
| 128 | 151 |
{
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| 129 |
switch(unit) {
|
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| 130 |
case UNIT_RX: return _clock->get_rx_dboard_clock_rates();
|
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| 131 |
case UNIT_TX: return _clock->get_tx_dboard_clock_rates();
|
|
| 132 |
default: UHD_THROW_INVALID_CODE_PATH();
|
|
| 152 |
std::vector<double> rates;
|
|
| 153 |
if (unit == UNIT_RX && _rx_dboard_id == dbsrx_classic_id){
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| 154 |
for (size_t div = 1; div <= 127; div++)
|
|
| 155 |
rates.push_back(_clock->get_master_clock_freq() / div);
|
|
| 133 | 156 |
} |
| 157 |
else{
|
|
| 158 |
rates.push_back(_clock->get_master_clock_freq()); |
|
| 159 |
} |
|
| 160 |
return rates; |
|
| 134 | 161 |
} |
| 135 | 162 |
|
| 136 | 163 |
double usrp1_dboard_iface::get_clock_rate(unit_t unit) |
| ... | ... | |
| 138 | 165 |
return _clock_rates[unit]; |
| 139 | 166 |
} |
| 140 | 167 |
|
| 141 |
void usrp1_dboard_iface::set_clock_enabled(unit_t unit, bool enb)
|
|
| 168 |
void usrp1_dboard_iface::set_clock_enabled(unit_t, bool)
|
|
| 142 | 169 |
{
|
| 143 |
switch(unit) {
|
|
| 144 |
case UNIT_RX: return _clock->enable_rx_dboard_clock(enb); |
|
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case UNIT_TX: return _clock->enable_tx_dboard_clock(enb); |
|
| 146 |
} |
|
| 170 |
//TODO we can only enable for special case anyway... |
|
| 147 | 171 |
} |
| 148 | 172 |
|
| 149 | 173 |
/*********************************************************************** |
| ... | ... | |
| 241 | 265 |
_iface->poke32(FR_ATR_RXVAL_1, value); |
| 242 | 266 |
else if (_dboard_slot == usrp1_impl::DBOARD_SLOT_B) |
| 243 | 267 |
_iface->poke32(FR_ATR_RXVAL_3, value); |
| 244 |
break;
|
|
| 268 |
break; |
|
| 245 | 269 |
case UNIT_TX: |
| 246 | 270 |
if (_dboard_slot == usrp1_impl::DBOARD_SLOT_A) |
| 247 | 271 |
_iface->poke32(FR_ATR_TXVAL_0, value); |
| ... | ... | |
| 265 | 289 |
switch(unit) {
|
| 266 | 290 |
case dboard_iface::UNIT_TX: |
| 267 | 291 |
if (slot == usrp1_impl::DBOARD_SLOT_A) |
| 268 |
return SPI_ENABLE_TX_A;
|
|
| 292 |
return SPI_ENABLE_TX_A; |
|
| 269 | 293 |
else if (slot == usrp1_impl::DBOARD_SLOT_B) |
| 270 | 294 |
return SPI_ENABLE_TX_B; |
| 271 | 295 |
else |
| 272 | 296 |
break; |
| 273 | 297 |
case dboard_iface::UNIT_RX: |
| 274 | 298 |
if (slot == usrp1_impl::DBOARD_SLOT_A) |
| 275 |
return SPI_ENABLE_RX_A;
|
|
| 299 |
return SPI_ENABLE_RX_A; |
|
| 276 | 300 |
else if (slot == usrp1_impl::DBOARD_SLOT_B) |
| 277 | 301 |
return SPI_ENABLE_RX_B; |
| 278 | 302 |
else |
| b/host/lib/usrp/usrp1/dboard_impl.cpp | ||
|---|---|---|
| 67 | 67 |
|
| 68 | 68 |
//create a new dboard interface and manager |
| 69 | 69 |
_dboard_ifaces[dboard_slot] = make_dboard_iface( |
| 70 |
_iface, _clock_ctrl, _codec_ctrls[dboard_slot], dboard_slot |
|
| 70 |
_iface, _clock_ctrl, _codec_ctrls[dboard_slot], |
|
| 71 |
dboard_slot, _rx_db_eeproms[dboard_slot].id |
|
| 71 | 72 |
); |
| 72 | 73 |
|
| 73 | 74 |
_dboard_managers[dboard_slot] = dboard_manager::make( |
| b/host/lib/usrp/usrp1/usrp1_impl.hpp | ||
|---|---|---|
| 25 | 25 |
#include <uhd/types/otw_type.hpp> |
| 26 | 26 |
#include <uhd/types/clock_config.hpp> |
| 27 | 27 |
#include <uhd/types/stream_cmd.hpp> |
| 28 |
#include <uhd/usrp/dboard_id.hpp> |
|
| 28 | 29 |
#include <uhd/usrp/subdev_spec.hpp> |
| 29 | 30 |
#include <uhd/usrp/dboard_eeprom.hpp> |
| 30 | 31 |
#include <uhd/usrp/dboard_manager.hpp> |
| ... | ... | |
| 45 | 46 |
typedef boost::function<void(const wax::obj &, const wax::obj &)> set_t; |
| 46 | 47 |
typedef boost::shared_ptr<wax_obj_proxy> sptr; |
| 47 | 48 |
|
| 48 |
static sptr make(const get_t &get, const set_t &set) |
|
| 49 |
{
|
|
| 49 |
static sptr make(const get_t &get, const set_t &set){
|
|
| 50 | 50 |
return sptr(new wax_obj_proxy(get, set)); |
| 51 | 51 |
} |
| 52 | 52 |
|
| ... | ... | |
| 102 | 102 |
* \param clock the clock control interface |
| 103 | 103 |
* \param codec the codec control interface |
| 104 | 104 |
* \param dboard_slot the slot identifier |
| 105 |
* \param rx_dboard_id the db id for the rx board (used for evil dbsrx purposes) |
|
| 105 | 106 |
* \return a sptr to a new dboard interface |
| 106 | 107 |
*/ |
| 107 | 108 |
static uhd::usrp::dboard_iface::sptr make_dboard_iface( |
| 108 | 109 |
usrp1_iface::sptr iface, |
| 109 | 110 |
usrp1_clock_ctrl::sptr clock, |
| 110 | 111 |
usrp1_codec_ctrl::sptr codec, |
| 111 |
dboard_slot_t dboard_slot |
|
| 112 |
dboard_slot_t dboard_slot, |
|
| 113 |
const uhd::usrp::dboard_id_t &rx_dboard_id |
|
| 112 | 114 |
); |
| 113 | 115 |
|
| 114 | 116 |
//interface to ioctls and file descriptor |
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