Revision 9fa6105a
| b/usrp2/top/u2_rev3/u2_rev3.v | ||
|---|---|---|
| 203 | 203 |
reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; |
| 204 | 204 |
reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; |
| 205 | 205 |
|
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// ADC A and B are swapped in schematic to facilitate clean layout |
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always @(posedge dsp_clk) |
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begin |
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adc_a_reg1 <= adc_b; // I and Q on RX are swapped in layout
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|
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adc_a_reg1 <= adc_b; |
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adc_b_reg1 <= adc_a; |
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adc_ovf_a_reg1 <= adc_ovf_b; |
| 211 | 212 |
adc_ovf_b_reg1 <= adc_ovf_a; |
| ... | ... | |
| 327 | 328 |
end |
| 328 | 329 |
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wire [15:0] dac_a_int, dac_b_int; |
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always @(negedge dsp_clk) dac_a <= dac_a_int; |
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always @(negedge dsp_clk) dac_b <= dac_b_int; |
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// DAC A and B are swapped in schematic to facilitate clean layout |
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// DAC A is also inverted in schematic to facilitate clean layout |
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always @(negedge dsp_clk) dac_a <= ~dac_b_int; |
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always @(negedge dsp_clk) dac_b <= dac_a_int; |
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| 332 | 335 |
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/* |
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OFDDRRSE OFDDRRSE_serdes_inst |
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