Revision 8b377a89

b/host/docs/usrp_e1xx.rst
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For the correct clock settings, call usrp->set_master_clock_rate(rate)


  		




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before any other parameters are set in your application.


  		




  
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


  		




  
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Clock rate recovery - unbricking


  		




  
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^


  		




  
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It is possible to set a clock rate such that the UHD can no longer communicate with the FPGA.


  		




  
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When this occurs, it is necessary to use the usrp-e-utility to recover the clock generator.


  		




  
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The recovery utility works by loading a special pass-through FPGA image so the computer


  		




  
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can talk directly to the clock generator over a SPI interface.


  		




  
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Run the following commands to restore the clock generator to a usable state:


  		




  
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::


  		




  
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    cd <prefix>/share/uhd/usrp_e_utilities


  		




  
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    ./usrp-e-utility --fpga=../images/usrp_e100_pt_fpga.bin --reclk


  		












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