uhd

## Status (0) Read

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pwr                   0[6]          0       not_reset, reset

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## I/Q Filter DAC (1) Read

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#include <uhd/utils/static.hpp>

#include <uhd/utils/assert.hpp>

#include <uhd/utils/algorithm.hpp>

#include <uhd/types/ranges.hpp>

#include <uhd/types/dict.hpp>

#include <uhd/usrp/subdev_props.hpp>

/***********************************************************************

 * The DBSRX constants

 **********************************************************************/

static const freq_range_t dbsrx_freq_range(0.8e9, 2.4e9);

        for(boost::uint8_t start_addr=start_reg; start_addr <= stop_reg; start_addr += sizeof(boost::uint32_t)){

            int num_bytes = int(stop_reg - start_addr + 1) > int(sizeof(boost::uint32_t)) ? sizeof(boost::uint32_t) : stop_reg - start_addr + 1;

            //create buffer for register data

            byte_vector_t regs_vector(num_bytes);

            for(boost::uint8_t i=0; i < num_bytes; i++){

                if (i + start_addr >= status_addr){

                    _max2118_read_regs.set_reg(i + start_addr, regs_vector[i]);

                }

                if(dbsrx_debug) std::cerr << boost::format(

                    "DBSRX: read reg 0x%02x, value 0x%04x, start_addr = 0x%04x, num_bytes %d"

     * \return true for locked

     */

    bool get_locked(void){

        //mask and return lock detect

        bool locked = 5 >= _max2118_read_regs.adc && _max2118_read_regs.adc >= 2;

    return dboard_base::sptr(new dbsrx(args, 0x67));

}

UHD_STATIC_BLOCK(reg_dbsrx_dboard){

    //register the factory function for the rx dbid

    dboard_manager::register_dboard(0x000D, &make_dbsrx, "DBSRX");

}

/***********************************************************************

 * Structors

 **********************************************************************/

dbsrx::dbsrx(ctor_args_t args, boost::uint8_t max2118_addr) : rx_dboard_base(args){

    //enable only the clocks we need

    this->get_iface()->set_clock_enabled(dboard_iface::UNIT_RX, true);

    //send initial register settings

    this->send_reg(0x0, 0x5);

    set_lo_freq(dbsrx_freq_range.min);

    BOOST_FOREACH(const std::string &name, dbsrx_gain_ranges.keys()){

        set_gain(dbsrx_gain_ranges[name].min, name);

    }

}

dbsrx::~dbsrx(void){

    target_freq = std::clip(target_freq, dbsrx_freq_range.min, dbsrx_freq_range.max);

    double actual_freq=0.0, pfd_freq=0.0, ref_clock=0.0;

    //choose refclock

    std::vector<double> clock_rates = this->get_iface()->get_clock_rates(dboard_iface::UNIT_RX);

    BOOST_FOREACH(ref_clock, std::reversed(std::sorted(clock_rates))){

        //choose R

        for(r = 0; r <= 6; r += 1) {

    } 

    //Assert because we failed to find a suitable combination of ref_clock, R and N 

    UHD_ASSERT_THROW((pfd_freq < dbsrx_pfd_freq_range.min) or (pfd_freq > dbsrx_pfd_freq_range.max));

    UHD_ASSERT_THROW((N < 256) or (N > 32768));

    done_loop:

    //compute resulting output frequency

    actual_freq = pfd_freq * N;

    //apply ref_clock, R, and N settings

    this->get_iface()->set_clock_rate(dboard_iface::UNIT_RX, ref_clock);

    ref_clock = this->get_iface()->get_clock_rate(dboard_iface::UNIT_RX);

    _max2118_write_regs.r_divider = (max2118_write_regs_t::r_divider_t) r;

    _max2118_write_regs.set_n_divider(N);

    _max2118_write_regs.ade_vco_ade_read = max2118_write_regs_t::ADE_VCO_ADE_READ_ENABLED;

    //compute prescaler variables

    int scaler = actual_freq > 1125e6 ? 2 : 4;

    _max2118_write_regs.div2 = scaler == 4 ? max2118_write_regs_t::DIV2_DIV4 : max2118_write_regs_t::DIV2_DIV2;

    //compute vco frequency and select vco

    double vco_freq = actual_freq * scaler;

    if (vco_freq < 2433e6)

    else if (vco_freq < 2711e6)

    else if (vco_freq < 3025e6)

    else if (vco_freq < 3341e6)

    else if (vco_freq < 3727e6)

    else if (vco_freq < 4143e6)

    else if (vco_freq < 4493e6)

    else

    //check vtune for lock condition

    //if we are out of lock for chosen vco, change vco

    while ((_max2118_read_regs.adc == 0) or (_max2118_read_regs.adc == 7)){

        //vtune is too low, try lower frequency vco

        if (_max2118_read_regs.adc == 0){

            _max2118_write_regs.osc_band -= 1;

        }

        //vtune is too high, try higher frequency vco

        if (_max2118_read_regs.adc == 7){

            _max2118_write_regs.osc_band += 1;

        }

        //update vco selection and check vtune

        send_reg(0x2, 0x2);

        read_reg(0x0, 0x0);

    }

    //select charge pump bias current

    if (_max2118_read_regs.adc <= 2) _max2118_write_regs.cp_current = max2118_write_regs_t::CP_CURRENT_I_CP_100UA;

    else if (_max2118_read_regs.adc >= 5) _max2118_write_regs.cp_current = max2118_write_regs_t::CP_CURRENT_I_CP_400UA;

        << boost::format("    Target Freq=%fMHz\n") % (target_freq/1e6)

        << boost::format("    Actual Freq=%fMHz\n") % (_lo_freq/1e6)

        << std::endl;

}

/***********************************************************************

    gain = std::clip<float>(gain, dbsrx_gain_ranges["GC1"].min, dbsrx_gain_ranges["GC1"].max);

    //voltage level constants

    static const float slope = (max_volts-min_volts)/dbsrx_gain_ranges["GC1"].max;

    //calculate the voltage for the aux dac

void dbsrx::set_bandwidth(float bandwidth){

    //clip the input

    bandwidth = std::clip<float>(bandwidth, 4e6, 33e6);

    if (dbsrx_debug) std::cerr << boost::format(

        "DBSRX Filter Bandwidth: %f MHz, m: %d, f_dac: %d\n"

}

/***********************************************************************