Revision 88cc06c1

b/usrp2/gpif/gpif.v
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      .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy),
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      .debug(debug_wr) );
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   // join vita packets which are longer than one frame, drop frame padding
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   wire [18:0] 	  refr_data;
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   wire 	  refr_src_rdy, refr_dst_rdy;
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   packet_reframer tx_packet_reframer 
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     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
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      .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy),
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      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));
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   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
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     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
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      .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy),
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      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
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      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
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   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
b/usrp2/gpif/gpif_wr_tb.v
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   initial #1000 sys_rst = 0;
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   always #64 gpif_clk <= ~gpif_clk;
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   always #47.9 sys_clk <= ~sys_clk;
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   wire [18:0] data_int;
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   wire        src_rdy_int, dst_rdy_int;
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   gpif_wr gpif_write
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     (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), 
......
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      .gpif_full_d(DF), .gpif_full_c(CF),
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      .sys_clk(sys_clk), .sys_rst(sys_rst),
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      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy),
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      .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int),
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      .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) );
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   packet_reframer tx_packet_reframer 
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     (.clk(sys_clk), .reset(sys_rst), .clear(0),
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      .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
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      .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy));
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   always @(posedge sys_clk)
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     if(ctrl_src_rdy & ctrl_dst_rdy)
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       $display("CTRL: %x",ctrl_o);
......
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	repeat (1)
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	  begin
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	     WR <= 1;
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	     gpif_data <= 150;  // Length
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	     gpif_data <= 10;  // Length
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	     @(posedge gpif_clk);
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	     gpif_data <= 16'h00;
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	     @(posedge gpif_clk);
......
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	     repeat (20)
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	       @(posedge gpif_clk);
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	     WR <= 1;
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	     gpif_data <= 16'hFF;
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	     gpif_data <= 16'h5;
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	     @(posedge gpif_clk);
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	     repeat(254)
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	       begin
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		  gpif_data <= gpif_data - 1;
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		  @(posedge gpif_clk);
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	       end
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	  end
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     end // initial begin
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b/usrp2/gpif/packet_reframer.v
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// Join vita packets longer than one GPIF frame, drop padding on short frames
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module packet_reframer
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  (input clk, input reset, input clear,
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   input [18:0] data_i,
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   input src_rdy_i,
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   output dst_rdy_o,
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   output [18:0] data_o,
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   output src_rdy_o,
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   input dst_rdy_i);
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   reg [1:0] state;
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   reg [15:0] length;
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   localparam RF_IDLE = 0;
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   localparam RF_PKT = 1;
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   localparam RF_DUMP = 2;
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   always @(posedge clk)
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     if(reset | clear)
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       state <= 0;
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     else
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       if(src_rdy_i & dst_rdy_i)
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	 case(state)
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	   RF_IDLE :
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	     begin
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		length <= {data_i[14:0],1'b0};
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		state <= RF_PKT;
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	     end
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	   RF_PKT :
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	     begin
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		if(length == 2)
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		  if(data_i[17])
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		    state <= RF_IDLE;
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		  else
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		    state <= RF_DUMP;
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		else
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		  length <= length - 1;
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	     end
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	   RF_DUMP :
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	     if(data_i[17])
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	       state <= RF_IDLE;
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	   default :
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	     state<= RF_IDLE;
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	 endcase // case (state)
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   assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok
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   assign src_rdy_o = src_rdy_i & (state != RF_DUMP);
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   wire occ_out = 0;
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   wire eof_out = (state == RF_PKT) & (length == 2);
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   wire sof_out = (state == RF_IDLE);
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   wire [15:0] data_out = data_i[15:0];
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   assign data_o = {occ_out, eof_out, sof_out, data_out};
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endmodule // packet_reframer
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