Revision 84b42223
| ID | 84b42223ce7d119ef89ffa4030c904c1b8efc243 |
Modified phase shift of DCM1 to -64 which is intended to give more timing margin on reads from the SRAM at the expense of Writes to the SRAM.
Tested to be at least as stable as a phase shift of 12 and beter looking timing on the logic analyzer.
Signals driven by the FPGA are observed changing on the SRAM pins about 4 nS after the rising edge of the RAM clock.
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