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root / usrp2 / sdr_lib / dsp_core_rx.v @ 7c057ae2

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module dsp_core_rx
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  #(parameter BASE = 160)
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  (input clk, input rst,
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   input set_stb, input [7:0] set_addr, input [31:0] set_data,
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   input [13:0] adc_a, input adc_ovf_a,
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   input [13:0] adc_b, input adc_ovf_b,
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   input [15:0] io_rx,
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   output [31:0] sample,
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   input run,
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   output strobe,
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   output [31:0] debug
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   );
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   wire [15:0] scale_i, scale_q;
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   wire [13:0] adc_a_ofs, adc_b_ofs;
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   reg [13:0] adc_i, adc_q;
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   wire [31:0] phase_inc;
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   reg [31:0]  phase;
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   wire [35:0] prod_i, prod_q;
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   wire [23:0] i_cordic, q_cordic;
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   wire [23:0] i_cic, q_cic;
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   wire [17:0] i_cic_scaled, q_cic_scaled;
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   wire [17:0] i_hb1, q_hb1;
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   wire [17:0] i_hb2, q_hb2;
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   wire [15:0] i_out, q_out;
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   wire        strobe_cic, strobe_hb1, strobe_hb2;
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   wire        enable_hb1, enable_hb2;
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   wire [7:0]  cic_decim_rate;
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   wire [31:10] UNUSED_1;
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   wire [31:4] 	UNUSED_2;
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   wire [31:2] 	UNUSED_3;
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   setting_reg #(.my_addr(BASE+0)) sr_0
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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      .in(set_data),.out(phase_inc),.changed());
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   setting_reg #(.my_addr(BASE+1)) sr_1
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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      .in(set_data),.out({scale_i,scale_q}),.changed());
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   setting_reg #(.my_addr(BASE+2)) sr_2
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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      .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());
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   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
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     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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      .adc_in(adc_a),.adc_out(adc_a_ofs));
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   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
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     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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      .adc_in(adc_b),.adc_out(adc_b_ofs));
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   wire [7:0]  muxctrl;
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   setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
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   wire [1:0] gpio_ena;
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   setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
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   always @(posedge clk)
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     case(muxctrl[3:0])		// The I mapping
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       0: adc_i <= adc_a_ofs;
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       1: adc_i <= adc_b_ofs;
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       2: adc_i <= 0;
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       default: adc_i <= 0;
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     endcase // case (muxctrl[3:0])
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   always @(posedge clk)
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     case(muxctrl[7:4])		// The Q mapping
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       0: adc_q <= adc_a_ofs;
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       1: adc_q <= adc_b_ofs;
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       2: adc_q <= 0;
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       default: adc_q <= 0;
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     endcase // case (muxctrl[7:4])
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   always @(posedge clk)
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     if(rst)
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       phase <= 0;
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     else if(~run)
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       phase <= 0;
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     else
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       phase <= phase + phase_inc;
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   MULT18X18S mult_i
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     (.P(prod_i),    // 36-bit multiplier output
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      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
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      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
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      .C(clk),    // Clock input
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      .CE(1),  // Clock enable input
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      .R(rst)     // Synchronous reset input
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      );
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   MULT18X18S mult_q
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     (.P(prod_q),    // 36-bit multiplier output
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      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
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      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
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      .C(clk),    // Clock input
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      .CE(1),  // Clock enable input
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      .R(rst)     // Synchronous reset input
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      ); 
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   cordic_z24 #(.bitwidth(24))
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     cordic(.clock(clk), .reset(rst), .enable(run),
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	    .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
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	    .xo(i_cordic),.yo(q_cordic),.zo() );
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   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
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			   .strobe_fast(1),.strobe_slow(strobe_cic) );
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   cic_decim #(.bw(24))
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     decim_i (.clock(clk),.reset(rst),.enable(run),
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	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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	      .signal_in(i_cordic),.signal_out(i_cic));
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   cic_decim #(.bw(24))
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     decim_q (.clock(clk),.reset(rst),.enable(run),
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	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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	      .signal_in(q_cordic),.signal_out(q_cic));
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   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
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   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
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   reg 	       strobe_cic_d1;
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   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
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   small_hb_dec #(.WIDTH(18)) small_hb_i
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     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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      .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
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   small_hb_dec #(.WIDTH(18)) small_hb_q
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     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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      .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
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   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
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   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
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     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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      .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
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   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
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     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
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   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
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   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
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   // Streaming GPIO
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   //
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   // io_rx[15] => I channel LSB if gpio_ena[0] high
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   // io_rx[14] => Q channel LSB if gpio_ena[1] high
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   reg [31:0] sample_reg;
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   always @(posedge clk)
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     begin
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	sample_reg[31:17] <= i_out[15:1];
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	sample_reg[15:1]  <= q_out[15:1];
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	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
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	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
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     end
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   assign      sample = sample_reg;
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   assign      strobe = strobe_hb2;
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   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
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endmodule // dsp_core_rx