Revision 7c057ae2 usrp2/sdr_lib/dsp_core_rx.v

b/usrp2/sdr_lib/dsp_core_rx.v
57 57 
     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
58 58 
      .adc_in(adc_b),.adc_out(adc_b_ofs));
59 59 

  		





  60
  
  
    
   wire [3:0]  muxctrl;


  		





  61
  
  
    
   setting_reg #(.my_addr(BASE+5)) sr_8


  		





  
  60
  
    
   wire [7:0]  muxctrl;


  		





  
  61
  
    
   setting_reg #(.my_addr(BASE+5), .width(8)) sr_8


  		





  62
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),


  		





  63
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      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());


  		





  64
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  65
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   wire [1:0] gpio_ena;


  		





  66
  
  
    
   setting_reg #(.my_addr(BASE+6)) sr_9


  		





  
  66
  
    
   setting_reg #(.my_addr(BASE+6), .width(2)) sr_9


  		





  67
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     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),


  		





  68
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      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());


  		





  69
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  70
  
  
    
   // The TVRX connects to what is called adc_b, thus A and B are


  		





  71
  
  
    
   // swapped throughout the design.


  		





  72
  
  
    
   //


  		





  73
  
  
    
   // In the interest of expediency and keeping the s/w sane, we just remap them here.


  		





  74
  
  
    
   // The I & Q fields are mapped the same:


  		





  75
  
  
    
   // 0 -> "the real A" (as determined by the TVRX)


  		





  76
  
  
    
   // 1 -> "the real B"


  		





  77
  
  
    
   // 2 -> const zero


  		





  78
  
  
    
   


  		





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   always @(posedge clk)


  		





  80
  
  
    
     case(muxctrl[1:0])		// The I mapping


  		





  81
  
  
    
       0: adc_i <= adc_b_ofs;	// "the real A"


  		





  82
  
  
    
       1: adc_i <= adc_a_ofs;


  		





  
  71
  
    
     case(muxctrl[3:0])		// The I mapping


  		





  
  72
  
    
       0: adc_i <= adc_a_ofs;


  		





  
  73
  
    
       1: adc_i <= adc_b_ofs;


  		





  83
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       2: adc_i <= 0;


  		





  84
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       default: adc_i <= 0;


  		





  85
  
  
    
     endcase // case(muxctrl[1:0])


  		





  86
  
  
    
          


  		





  
  76
  
    
     endcase // case (muxctrl[3:0])


  		





  
  77
  
    
   


  		





  87
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   always @(posedge clk)


  		





  88
  
  
    
     case(muxctrl[3:2])		// The Q mapping


  		





  89
  
  
    
       0: adc_q <= adc_b_ofs;	// "the real A"


  		





  90
  
  
    
       1: adc_q <= adc_a_ofs;


  		





  
  79
  
    
     case(muxctrl[7:4])		// The Q mapping


  		





  
  80
  
    
       0: adc_q <= adc_a_ofs;


  		





  
  81
  
    
       1: adc_q <= adc_b_ofs;


  		





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       2: adc_q <= 0;


  		





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       default: adc_q <= 0;


  		





  93
  
  
    
     endcase // case(muxctrl[3:2])


  		





  94
  
  
    
       


  		





  
  84
  
    
     endcase // case (muxctrl[7:4])


  		





  
  85
  
    
          


  		





  95
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   always @(posedge clk)


  		





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     if(rst)


  		





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       phase <= 0;


  		












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