Revision 7c057ae2
| b/usrp2/sdr_lib/dsp_core_rx.v | ||
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| 57 | 57 |
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), |
| 58 | 58 |
.adc_in(adc_b),.adc_out(adc_b_ofs)); |
| 59 | 59 |
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wire [3:0] muxctrl;
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setting_reg #(.my_addr(BASE+5)) sr_8 |
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wire [7:0] muxctrl;
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setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
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| 62 | 62 |
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), |
| 63 | 63 |
.in(set_data),.out({UNUSED_2,muxctrl}),.changed());
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| 64 | 64 |
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| 65 | 65 |
wire [1:0] gpio_ena; |
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setting_reg #(.my_addr(BASE+6)) sr_9 |
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setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
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| 67 | 67 |
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), |
| 68 | 68 |
.in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
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| 69 | 69 |
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// The TVRX connects to what is called adc_b, thus A and B are |
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// swapped throughout the design. |
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// |
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// In the interest of expediency and keeping the s/w sane, we just remap them here. |
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// The I & Q fields are mapped the same: |
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// 0 -> "the real A" (as determined by the TVRX) |
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// 1 -> "the real B" |
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// 2 -> const zero |
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| 79 | 70 |
always @(posedge clk) |
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case(muxctrl[1:0]) // The I mapping
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0: adc_i <= adc_b_ofs; // "the real A"
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1: adc_i <= adc_a_ofs;
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case(muxctrl[3:0]) // The I mapping
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0: adc_i <= adc_a_ofs;
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1: adc_i <= adc_b_ofs;
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| 83 | 74 |
2: adc_i <= 0; |
| 84 | 75 |
default: adc_i <= 0; |
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endcase // case(muxctrl[1:0])
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endcase // case (muxctrl[3:0])
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| 87 | 78 |
always @(posedge clk) |
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case(muxctrl[3:2]) // The Q mapping
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0: adc_q <= adc_b_ofs; // "the real A"
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1: adc_q <= adc_a_ofs;
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case(muxctrl[7:4]) // The Q mapping
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0: adc_q <= adc_a_ofs;
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1: adc_q <= adc_b_ofs;
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| 91 | 82 |
2: adc_q <= 0; |
| 92 | 83 |
default: adc_q <= 0; |
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endcase // case(muxctrl[3:2])
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endcase // case (muxctrl[7:4])
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| 95 | 86 |
always @(posedge clk) |
| 96 | 87 |
if(rst) |
| 97 | 88 |
phase <= 0; |
| b/usrp2/top/u2_rev3/u2_core_udp.v | ||
|---|---|---|
| 425 | 425 |
cycle_count <= cycle_count + 1; |
| 426 | 426 |
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| 427 | 427 |
//compatibility number -> increment when the fpga has been sufficiently altered |
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localparam compat_num = 32'd1;
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localparam compat_num = 32'd2;
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| 429 | 429 |
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| 430 | 430 |
wb_readback_mux buff_pool_status |
| 431 | 431 |
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), |
| b/usrp2/top/u2_rev3/u2_rev3.v | ||
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| 205 | 205 |
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| 206 | 206 |
always @(posedge dsp_clk) |
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begin |
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adc_a_reg1 <= adc_a;
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adc_b_reg1 <= adc_b;
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adc_ovf_a_reg1 <= adc_ovf_a;
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adc_ovf_b_reg1 <= adc_ovf_b;
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adc_a_reg1 <= adc_b; // I and Q on RX are swapped in layout
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adc_b_reg1 <= adc_a;
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adc_ovf_a_reg1 <= adc_ovf_b;
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adc_ovf_b_reg1 <= adc_ovf_a;
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| 212 | 212 |
end |
| 213 | 213 |
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| 214 | 214 |
always @(posedge dsp_clk) |
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