root / firmware / fx2 / include / fx2regs.h @ 70eae1d2
History | View | Annotate | Download (31.1 kB)
| 1 |
/* -*- c++ -*- */
|
|---|---|
| 2 |
/*
|
| 3 |
* Copyright 2003 Free Software Foundation, Inc.
|
| 4 |
*
|
| 5 |
* This file is part of GNU Radio
|
| 6 |
*
|
| 7 |
* GNU Radio is free software; you can redistribute it and/or modify
|
| 8 |
* it under the terms of the GNU General Public License as published by
|
| 9 |
* the Free Software Foundation; either version 3, or (at your option)
|
| 10 |
* any later version.
|
| 11 |
*
|
| 12 |
* GNU Radio is distributed in the hope that it will be useful,
|
| 13 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 14 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 15 |
* GNU General Public License for more details.
|
| 16 |
*
|
| 17 |
* You should have received a copy of the GNU General Public License
|
| 18 |
* along with GNU Radio; see the file COPYING. If not, write to
|
| 19 |
* the Free Software Foundation, Inc., 51 Franklin Street,
|
| 20 |
* Boston, MA 02110-1301, USA.
|
| 21 |
*/
|
| 22 |
|
| 23 |
/*
|
| 24 |
//-----------------------------------------------------------------------------
|
| 25 |
// File: FX2regs.h
|
| 26 |
// Contents: EZ-USB FX2 register declarations and bit mask definitions.
|
| 27 |
//
|
| 28 |
// $Archive: /USB/Target/Inc/fx2regs.h $
|
| 29 |
// $Date$
|
| 30 |
// $Revision$
|
| 31 |
//
|
| 32 |
//
|
| 33 |
// Copyright (c) 2000 Cypress Semiconductor, All rights reserved
|
| 34 |
//-----------------------------------------------------------------------------
|
| 35 |
*/
|
| 36 |
|
| 37 |
|
| 38 |
#ifndef FX2REGS_H /* Header Sentry */ |
| 39 |
#define FX2REGS_H
|
| 40 |
|
| 41 |
#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h |
| 42 |
|
| 43 |
/*
|
| 44 |
//-----------------------------------------------------------------------------
|
| 45 |
// FX2 Related Register Assignments
|
| 46 |
//-----------------------------------------------------------------------------
|
| 47 |
|
| 48 |
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
|
| 49 |
// address allocation by using "#define ALLOCATE_EXTERN".
|
| 50 |
// When using "#define ALLOCATE_EXTERN", you get (for instance):
|
| 51 |
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
|
| 52 |
// Such lines are created from FX2.h by using the preprocessor.
|
| 53 |
// Incidently, these lines will not generate any space in the resulting hex
|
| 54 |
// file; they just bind the symbols to the addresses for compilation.
|
| 55 |
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
|
| 56 |
// i.e. fw.c or a stand-alone C source file.
|
| 57 |
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
|
| 58 |
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
|
| 59 |
// This uses the concatenation operator "##" to insert a comment "//"
|
| 60 |
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
|
| 61 |
*/
|
| 62 |
|
| 63 |
|
| 64 |
#ifdef ALLOCATE_EXTERN
|
| 65 |
#define EXTERN
|
| 66 |
#define _AT_(a) at a
|
| 67 |
#else
|
| 68 |
#define EXTERN extern |
| 69 |
#define _AT_ ;/ ## / |
| 70 |
#endif
|
| 71 |
|
| 72 |
typedef unsigned char BYTE; |
| 73 |
typedef unsigned short WORD; |
| 74 |
|
| 75 |
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; |
| 76 |
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ; |
| 77 |
|
| 78 |
// General Configuration
|
| 79 |
|
| 80 |
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status |
| 81 |
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration |
| 82 |
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments |
| 83 |
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments |
| 84 |
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state |
| 85 |
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint |
| 86 |
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H |
| 87 |
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L |
| 88 |
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2 |
| 89 |
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities |
| 90 |
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision |
| 91 |
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control |
| 92 |
|
| 93 |
// Endpoint Configuration
|
| 94 |
|
| 95 |
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration |
| 96 |
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration |
| 97 |
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration |
| 98 |
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration |
| 99 |
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration |
| 100 |
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration |
| 101 |
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration |
| 102 |
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration |
| 103 |
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration |
| 104 |
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration |
| 105 |
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only) |
| 106 |
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only) |
| 107 |
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only) |
| 108 |
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only) |
| 109 |
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only) |
| 110 |
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only) |
| 111 |
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only) |
| 112 |
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only) |
| 113 |
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H |
| 114 |
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L |
| 115 |
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H |
| 116 |
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L |
| 117 |
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H |
| 118 |
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L |
| 119 |
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H |
| 120 |
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L |
| 121 |
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3) |
| 122 |
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3) |
| 123 |
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3) |
| 124 |
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3) |
| 125 |
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End |
| 126 |
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End |
| 127 |
|
| 128 |
// Interrupts
|
| 129 |
|
| 130 |
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable |
| 131 |
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request |
| 132 |
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable |
| 133 |
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request |
| 134 |
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable |
| 135 |
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request |
| 136 |
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable |
| 137 |
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request |
| 138 |
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable |
| 139 |
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request |
| 140 |
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable |
| 141 |
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request |
| 142 |
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables |
| 143 |
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests |
| 144 |
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables |
| 145 |
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests |
| 146 |
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable |
| 147 |
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request |
| 148 |
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables |
| 149 |
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests |
| 150 |
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit |
| 151 |
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0] |
| 152 |
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector |
| 153 |
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector |
| 154 |
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup |
| 155 |
|
| 156 |
// Input/Output
|
| 157 |
|
| 158 |
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration |
| 159 |
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration |
| 160 |
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration |
| 161 |
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status |
| 162 |
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data |
| 163 |
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control |
| 164 |
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access |
| 165 |
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access |
| 166 |
|
| 167 |
#define EXTAUTODAT1 XAUTODAT1
|
| 168 |
#define EXTAUTODAT2 XAUTODAT2
|
| 169 |
|
| 170 |
// USB Control
|
| 171 |
|
| 172 |
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status |
| 173 |
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend |
| 174 |
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity |
| 175 |
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control |
| 176 |
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H |
| 177 |
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L |
| 178 |
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7 |
| 179 |
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address |
| 180 |
|
| 181 |
// Endpoints
|
| 182 |
|
| 183 |
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H |
| 184 |
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L |
| 185 |
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count |
| 186 |
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count |
| 187 |
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H |
| 188 |
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L |
| 189 |
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H |
| 190 |
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L |
| 191 |
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H |
| 192 |
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L |
| 193 |
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H |
| 194 |
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L |
| 195 |
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status |
| 196 |
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status |
| 197 |
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status |
| 198 |
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status |
| 199 |
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status |
| 200 |
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status |
| 201 |
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status |
| 202 |
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags |
| 203 |
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags |
| 204 |
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags |
| 205 |
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags |
| 206 |
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H |
| 207 |
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L |
| 208 |
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H |
| 209 |
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L |
| 210 |
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H |
| 211 |
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L |
| 212 |
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H |
| 213 |
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L |
| 214 |
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte |
| 215 |
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte |
| 216 |
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode |
| 217 |
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data |
| 218 |
|
| 219 |
// GPIF
|
| 220 |
|
| 221 |
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector |
| 222 |
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode |
| 223 |
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states |
| 224 |
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive |
| 225 |
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H |
| 226 |
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L |
| 227 |
|
| 228 |
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3 |
| 229 |
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2 |
| 230 |
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1 |
| 231 |
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0 |
| 232 |
|
| 233 |
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility |
| 234 |
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) |
| 235 |
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility |
| 236 |
#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) |
| 237 |
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility |
| 238 |
#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) |
| 239 |
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility |
| 240 |
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD) |
| 241 |
|
| 242 |
// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
|
| 243 |
// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
|
| 244 |
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select |
| 245 |
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag |
| 246 |
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger |
| 247 |
// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
|
| 248 |
// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
|
| 249 |
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select |
| 250 |
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag |
| 251 |
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger |
| 252 |
// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
|
| 253 |
// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
|
| 254 |
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select |
| 255 |
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag |
| 256 |
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger |
| 257 |
// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
|
| 258 |
// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
|
| 259 |
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select |
| 260 |
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag |
| 261 |
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger |
| 262 |
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only) |
| 263 |
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac |
| 264 |
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger |
| 265 |
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG |
| 266 |
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states |
| 267 |
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles |
| 268 |
|
| 269 |
// UDMA
|
| 270 |
|
| 271 |
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state |
| 272 |
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria |
| 273 |
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state |
| 274 |
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state |
| 275 |
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ; |
| 276 |
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe |
| 277 |
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge |
| 278 |
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe |
| 279 |
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift |
| 280 |
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte |
| 281 |
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte |
| 282 |
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only |
| 283 |
|
| 284 |
|
| 285 |
// Debug/Test
|
| 286 |
|
| 287 |
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug |
| 288 |
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration |
| 289 |
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes |
| 290 |
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override |
| 291 |
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM |
| 292 |
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals |
| 293 |
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs |
| 294 |
|
| 295 |
// Endpoint Buffers
|
| 296 |
|
| 297 |
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer |
| 298 |
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer |
| 299 |
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer |
| 300 |
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT) |
| 301 |
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT) |
| 302 |
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT) |
| 303 |
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT) |
| 304 |
|
| 305 |
#undef EXTERN
|
| 306 |
#undef _AT_
|
| 307 |
|
| 308 |
/*-----------------------------------------------------------------------------
|
| 309 |
Special Function Registers (SFRs)
|
| 310 |
The byte registers and bits defined in the following list are based
|
| 311 |
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
|
| 312 |
If you modify the register definitions below, please regenerate the file
|
| 313 |
"ezregs.inc" which includes the same basic information for assembly inclusion.
|
| 314 |
-----------------------------------------------------------------------------*/
|
| 315 |
|
| 316 |
sfr at 0x80 IOA;
|
| 317 |
sfr at 0x81 SP;
|
| 318 |
sfr at 0x82 DPL;
|
| 319 |
sfr at 0x83 DPH;
|
| 320 |
sfr at 0x84 DPL1;
|
| 321 |
sfr at 0x85 DPH1;
|
| 322 |
sfr at 0x86 DPS;
|
| 323 |
/* DPS */
|
| 324 |
sbit at 0x86+0 SEL; |
| 325 |
sfr at 0x87 PCON; /* PCON */ |
| 326 |
//sbit IDLE = 0x87+0;
|
| 327 |
//sbit STOP = 0x87+1;
|
| 328 |
//sbit GF0 = 0x87+2;
|
| 329 |
//sbit GF1 = 0x87+3;
|
| 330 |
//sbit SMOD0 = 0x87+7;
|
| 331 |
sfr at 0x88 TCON;
|
| 332 |
/* TCON */
|
| 333 |
sbit at 0x88+0 IT0; |
| 334 |
sbit at 0x88+1 IE0; |
| 335 |
sbit at 0x88+2 IT1; |
| 336 |
sbit at 0x88+3 IE1; |
| 337 |
sbit at 0x88+4 TR0; |
| 338 |
sbit at 0x88+5 TF0; |
| 339 |
sbit at 0x88+6 TR1; |
| 340 |
sbit at 0x88+7 TF1; |
| 341 |
sfr at 0x89 TMOD;
|
| 342 |
/* TMOD */
|
| 343 |
//sbit M00 = 0x89+0;
|
| 344 |
//sbit M10 = 0x89+1;
|
| 345 |
//sbit CT0 = 0x89+2;
|
| 346 |
//sbit GATE0 = 0x89+3;
|
| 347 |
//sbit M01 = 0x89+4;
|
| 348 |
//sbit M11 = 0x89+5;
|
| 349 |
//sbit CT1 = 0x89+6;
|
| 350 |
//sbit GATE1 = 0x89+7;
|
| 351 |
sfr at 0x8A TL0;
|
| 352 |
sfr at 0x8B TL1;
|
| 353 |
sfr at 0x8C TH0;
|
| 354 |
sfr at 0x8D TH1;
|
| 355 |
sfr at 0x8E CKCON;
|
| 356 |
/* CKCON */
|
| 357 |
//sbit MD0 = 0x89+0;
|
| 358 |
//sbit MD1 = 0x89+1;
|
| 359 |
//sbit MD2 = 0x89+2;
|
| 360 |
//sbit T0M = 0x89+3;
|
| 361 |
//sbit T1M = 0x89+4;
|
| 362 |
//sbit T2M = 0x89+5;
|
| 363 |
// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
|
| 364 |
/* CKCON */
|
| 365 |
//sbit WRS = 0x8F+0;
|
| 366 |
sfr at 0x90 IOB;
|
| 367 |
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320 |
| 368 |
/* EXIF */
|
| 369 |
//sbit USBINT = 0x91+4;
|
| 370 |
//sbit I2CINT = 0x91+5;
|
| 371 |
//sbit IE4 = 0x91+6;
|
| 372 |
//sbit IE5 = 0x91+7;
|
| 373 |
sfr at 0x92 MPAGE;
|
| 374 |
sfr at 0x98 SCON0;
|
| 375 |
/* SCON0 */
|
| 376 |
sbit at 0x98+0 RI; |
| 377 |
sbit at 0x98+1 TI; |
| 378 |
sbit at 0x98+2 RB8; |
| 379 |
sbit at 0x98+3 TB8; |
| 380 |
sbit at 0x98+4 REN; |
| 381 |
sbit at 0x98+5 SM2; |
| 382 |
sbit at 0x98+6 SM1; |
| 383 |
sbit at 0x98+7 SM0; |
| 384 |
sfr at 0x99 SBUF0;
|
| 385 |
|
| 386 |
sfr at 0x9A APTR1H;
|
| 387 |
sfr at 0x9B APTR1L;
|
| 388 |
sfr at 0x9C AUTODAT1;
|
| 389 |
sfr at 0x9D AUTOPTRH2;
|
| 390 |
sfr at 0x9E AUTOPTRL2;
|
| 391 |
sfr at 0x9F AUTODAT2;
|
| 392 |
sfr at 0xA0 IOC;
|
| 393 |
sfr at 0xA1 INT2CLR;
|
| 394 |
sfr at 0xA2 INT4CLR;
|
| 395 |
|
| 396 |
#define AUTOPTRH1 APTR1H
|
| 397 |
#define AUTOPTRL1 APTR1L
|
| 398 |
|
| 399 |
sfr at 0xA8 IE;
|
| 400 |
/* IE */
|
| 401 |
sbit at 0xA8+0 EX0; |
| 402 |
sbit at 0xA8+1 ET0; |
| 403 |
sbit at 0xA8+2 EX1; |
| 404 |
sbit at 0xA8+3 ET1; |
| 405 |
sbit at 0xA8+4 ES0; |
| 406 |
sbit at 0xA8+5 ET2; |
| 407 |
sbit at 0xA8+6 ES1; |
| 408 |
sbit at 0xA8+7 EA; |
| 409 |
|
| 410 |
sfr at 0xAA EP2468STAT;
|
| 411 |
/* EP2468STAT */
|
| 412 |
//sbit EP2E = 0xAA+0;
|
| 413 |
//sbit EP2F = 0xAA+1;
|
| 414 |
//sbit EP4E = 0xAA+2;
|
| 415 |
//sbit EP4F = 0xAA+3;
|
| 416 |
//sbit EP6E = 0xAA+4;
|
| 417 |
//sbit EP6F = 0xAA+5;
|
| 418 |
//sbit EP8E = 0xAA+6;
|
| 419 |
//sbit EP8F = 0xAA+7;
|
| 420 |
|
| 421 |
sfr at 0xAB EP24FIFOFLGS;
|
| 422 |
sfr at 0xAC EP68FIFOFLGS;
|
| 423 |
sfr at 0xAF AUTOPTRSETUP;
|
| 424 |
/* AUTOPTRSETUP */
|
| 425 |
// sbit EXTACC = 0xAF+0;
|
| 426 |
// sbit APTR1FZ = 0xAF+1;
|
| 427 |
// sbit APTR2FZ = 0xAF+2;
|
| 428 |
|
| 429 |
sfr at 0xB0 IOD;
|
| 430 |
sfr at 0xB1 IOE;
|
| 431 |
sfr at 0xB2 OEA;
|
| 432 |
sfr at 0xB3 OEB;
|
| 433 |
sfr at 0xB4 OEC;
|
| 434 |
sfr at 0xB5 OED;
|
| 435 |
sfr at 0xB6 OEE;
|
| 436 |
|
| 437 |
sfr at 0xB8 IP;
|
| 438 |
/* IP */
|
| 439 |
sbit at 0xB8+0 PX0; |
| 440 |
sbit at 0xB8+1 PT0; |
| 441 |
sbit at 0xB8+2 PX1; |
| 442 |
sbit at 0xB8+3 PT1; |
| 443 |
sbit at 0xB8+4 PS0; |
| 444 |
sbit at 0xB8+5 PT2; |
| 445 |
sbit at 0xB8+6 PS1; |
| 446 |
|
| 447 |
sfr at 0xBA EP01STAT;
|
| 448 |
sfr at 0xBB GPIFTRIG;
|
| 449 |
|
| 450 |
sfr at 0xBD GPIFSGLDATH;
|
| 451 |
sfr at 0xBE GPIFSGLDATLX;
|
| 452 |
sfr at 0xBF GPIFSGLDATLNOX;
|
| 453 |
|
| 454 |
sfr at 0xC0 SCON1;
|
| 455 |
/* SCON1 */
|
| 456 |
sbit at 0xC0+0 RI1; |
| 457 |
sbit at 0xC0+1 TI1; |
| 458 |
sbit at 0xC0+2 RB81; |
| 459 |
sbit at 0xC0+3 TB81; |
| 460 |
sbit at 0xC0+4 REN1; |
| 461 |
sbit at 0xC0+5 SM21; |
| 462 |
sbit at 0xC0+6 SM11; |
| 463 |
sbit at 0xC0+7 SM01; |
| 464 |
sfr at 0xC1 SBUF1;
|
| 465 |
sfr at 0xC8 T2CON;
|
| 466 |
/* T2CON */
|
| 467 |
sbit at 0xC8+0 CP_RL2; |
| 468 |
sbit at 0xC8+1 C_T2; |
| 469 |
sbit at 0xC8+2 TR2; |
| 470 |
sbit at 0xC8+3 EXEN2; |
| 471 |
sbit at 0xC8+4 TCLK; |
| 472 |
sbit at 0xC8+5 RCLK; |
| 473 |
sbit at 0xC8+6 EXF2; |
| 474 |
sbit at 0xC8+7 TF2; |
| 475 |
sfr at 0xCA RCAP2L;
|
| 476 |
sfr at 0xCB RCAP2H;
|
| 477 |
sfr at 0xCC TL2;
|
| 478 |
sfr at 0xCD TH2;
|
| 479 |
sfr at 0xD0 PSW;
|
| 480 |
/* PSW */
|
| 481 |
sbit at 0xD0+0 P; |
| 482 |
sbit at 0xD0+1 FL; |
| 483 |
sbit at 0xD0+2 OV; |
| 484 |
sbit at 0xD0+3 RS0; |
| 485 |
sbit at 0xD0+4 RS1; |
| 486 |
sbit at 0xD0+5 F0; |
| 487 |
sbit at 0xD0+6 AC; |
| 488 |
sbit at 0xD0+7 CY; |
| 489 |
sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 |
| 490 |
/* EICON */
|
| 491 |
sbit at 0xD8+3 INT6; |
| 492 |
sbit at 0xD8+4 RESI; |
| 493 |
sbit at 0xD8+5 ERESI; |
| 494 |
sbit at 0xD8+7 SMOD1; |
| 495 |
sfr at 0xE0 ACC;
|
| 496 |
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320 |
| 497 |
/* EIE */
|
| 498 |
sbit at 0xE8+0 EIUSB; |
| 499 |
sbit at 0xE8+1 EI2C; |
| 500 |
sbit at 0xE8+2 EIEX4; |
| 501 |
sbit at 0xE8+3 EIEX5; |
| 502 |
sbit at 0xE8+4 EIEX6; |
| 503 |
sfr at 0xF0 B;
|
| 504 |
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320 |
| 505 |
/* EIP */
|
| 506 |
sbit at 0xF8+0 PUSB; |
| 507 |
sbit at 0xF8+1 PI2C; |
| 508 |
sbit at 0xF8+2 EIPX4; |
| 509 |
sbit at 0xF8+3 EIPX5; |
| 510 |
sbit at 0xF8+4 EIPX6; |
| 511 |
|
| 512 |
/*-----------------------------------------------------------------------------
|
| 513 |
Bit Masks
|
| 514 |
-----------------------------------------------------------------------------*/
|
| 515 |
|
| 516 |
#define bmBIT0 1 |
| 517 |
#define bmBIT1 2 |
| 518 |
#define bmBIT2 4 |
| 519 |
#define bmBIT3 8 |
| 520 |
#define bmBIT4 16 |
| 521 |
#define bmBIT5 32 |
| 522 |
#define bmBIT6 64 |
| 523 |
#define bmBIT7 128 |
| 524 |
|
| 525 |
/* CPU Control & Status Register (CPUCS) */
|
| 526 |
#define bmPRTCSTB bmBIT5
|
| 527 |
#define bmCLKSPD (bmBIT4 | bmBIT3)
|
| 528 |
#define bmCLKSPD1 bmBIT4
|
| 529 |
#define bmCLKSPD0 bmBIT3
|
| 530 |
#define bmCLKINV bmBIT2
|
| 531 |
#define bmCLKOE bmBIT1
|
| 532 |
#define bm8051RES bmBIT0
|
| 533 |
/* Port Alternate Configuration Registers */
|
| 534 |
/* Port A (PORTACFG) */
|
| 535 |
#define bmFLAGD bmBIT7
|
| 536 |
#define bmINT1 bmBIT1
|
| 537 |
#define bmINT0 bmBIT0
|
| 538 |
/* Port C (PORTCCFG) */
|
| 539 |
#define bmGPIFA7 bmBIT7
|
| 540 |
#define bmGPIFA6 bmBIT6
|
| 541 |
#define bmGPIFA5 bmBIT5
|
| 542 |
#define bmGPIFA4 bmBIT4
|
| 543 |
#define bmGPIFA3 bmBIT3
|
| 544 |
#define bmGPIFA2 bmBIT2
|
| 545 |
#define bmGPIFA1 bmBIT1
|
| 546 |
#define bmGPIFA0 bmBIT0
|
| 547 |
/* Port E (PORTECFG) */
|
| 548 |
#define bmGPIFA8 bmBIT7
|
| 549 |
#define bmT2EX bmBIT6
|
| 550 |
#define bmINT6 bmBIT5
|
| 551 |
#define bmRXD1OUT bmBIT4
|
| 552 |
#define bmRXD0OUT bmBIT3
|
| 553 |
#define bmT2OUT bmBIT2
|
| 554 |
#define bmT1OUT bmBIT1
|
| 555 |
#define bmT0OUT bmBIT0
|
| 556 |
|
| 557 |
/* I2C Control & Status Register (I2CS) */
|
| 558 |
#define bmSTART bmBIT7
|
| 559 |
#define bmSTOP bmBIT6
|
| 560 |
#define bmLASTRD bmBIT5
|
| 561 |
#define bmID (bmBIT4 | bmBIT3)
|
| 562 |
#define bmBERR bmBIT2
|
| 563 |
#define bmACK bmBIT1
|
| 564 |
#define bmDONE bmBIT0
|
| 565 |
/* I2C Control Register (I2CTL) */
|
| 566 |
#define bmSTOPIE bmBIT1
|
| 567 |
#define bm400KHZ bmBIT0
|
| 568 |
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
|
| 569 |
#define bmIV4 bmBIT6
|
| 570 |
#define bmIV3 bmBIT5
|
| 571 |
#define bmIV2 bmBIT4
|
| 572 |
#define bmIV1 bmBIT3
|
| 573 |
#define bmIV0 bmBIT2
|
| 574 |
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
|
| 575 |
#define bmEP0ACK bmBIT6
|
| 576 |
#define bmHSGRANT bmBIT5
|
| 577 |
#define bmURES bmBIT4
|
| 578 |
#define bmSUSP bmBIT3
|
| 579 |
#define bmSUTOK bmBIT2
|
| 580 |
#define bmSOF bmBIT1
|
| 581 |
#define bmSUDAV bmBIT0
|
| 582 |
/* Breakpoint register (BREAKPT) */
|
| 583 |
#define bmBREAK bmBIT3
|
| 584 |
#define bmBPPULSE bmBIT2
|
| 585 |
#define bmBPEN bmBIT1
|
| 586 |
/* Interrupt 2 & 4 Setup (INTSETUP) */
|
| 587 |
#define bmAV2EN bmBIT3
|
| 588 |
#define bmINT4IN bmBIT1
|
| 589 |
#define bmAV4EN bmBIT0
|
| 590 |
/* USB Control & Status Register (USBCS) */
|
| 591 |
#define bmHSM bmBIT7
|
| 592 |
#define bmDISCON bmBIT3
|
| 593 |
#define bmNOSYNSOF bmBIT2
|
| 594 |
#define bmRENUM bmBIT1
|
| 595 |
#define bmSIGRESUME bmBIT0
|
| 596 |
/* Wakeup Control and Status Register (WAKEUPCS) */
|
| 597 |
#define bmWU2 bmBIT7
|
| 598 |
#define bmWU bmBIT6
|
| 599 |
#define bmWU2POL bmBIT5
|
| 600 |
#define bmWUPOL bmBIT4
|
| 601 |
#define bmDPEN bmBIT2
|
| 602 |
#define bmWU2EN bmBIT1
|
| 603 |
#define bmWUEN bmBIT0
|
| 604 |
/* End Point 0 Control & Status Register (EP0CS) */
|
| 605 |
#define bmHSNAK bmBIT7
|
| 606 |
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
|
| 607 |
#define bmEPBUSY bmBIT1
|
| 608 |
#define bmEPSTALL bmBIT0
|
| 609 |
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
|
| 610 |
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
|
| 611 |
#define bmEPFULL bmBIT3
|
| 612 |
#define bmEPEMPTY bmBIT2
|
| 613 |
/* Endpoint Status (EP2468STAT) SFR bits */
|
| 614 |
#define bmEP8FULL bmBIT7
|
| 615 |
#define bmEP8EMPTY bmBIT6
|
| 616 |
#define bmEP6FULL bmBIT5
|
| 617 |
#define bmEP6EMPTY bmBIT4
|
| 618 |
#define bmEP4FULL bmBIT3
|
| 619 |
#define bmEP4EMPTY bmBIT2
|
| 620 |
#define bmEP2FULL bmBIT1
|
| 621 |
#define bmEP2EMPTY bmBIT0
|
| 622 |
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
|
| 623 |
#define bmSDPAUTO bmBIT0
|
| 624 |
/* Endpoint Data Toggle Control (TOGCTL) */
|
| 625 |
#define bmQUERYTOGGLE bmBIT7
|
| 626 |
#define bmSETTOGGLE bmBIT6
|
| 627 |
#define bmRESETTOGGLE bmBIT5
|
| 628 |
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
|
| 629 |
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
|
| 630 |
#define bmEP8IBN bmBIT5
|
| 631 |
#define bmEP6IBN bmBIT4
|
| 632 |
#define bmEP4IBN bmBIT3
|
| 633 |
#define bmEP2IBN bmBIT2
|
| 634 |
#define bmEP1IBN bmBIT1
|
| 635 |
#define bmEP0IBN bmBIT0
|
| 636 |
|
| 637 |
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
|
| 638 |
#define bmEP8PING bmBIT7
|
| 639 |
#define bmEP6PING bmBIT6
|
| 640 |
#define bmEP4PING bmBIT5
|
| 641 |
#define bmEP2PING bmBIT4
|
| 642 |
#define bmEP1PING bmBIT3
|
| 643 |
#define bmEP0PING bmBIT2
|
| 644 |
#define bmIBN bmBIT0
|
| 645 |
|
| 646 |
/* Interface Configuration bits (IFCONFIG) */
|
| 647 |
#define bmIFCLKSRC bmBIT7 // set == INTERNAL |
| 648 |
#define bm3048MHZ bmBIT6 // set == 48 MHz |
| 649 |
#define bmIFCLKOE bmBIT5
|
| 650 |
#define bmIFCLKPOL bmBIT4
|
| 651 |
#define bmASYNC bmBIT3
|
| 652 |
#define bmGSTATE bmBIT2
|
| 653 |
#define bmIFCFG1 bmBIT1
|
| 654 |
#define bmIFCFG0 bmBIT0
|
| 655 |
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
|
| 656 |
#define bmIFGPIF bmIFCFG1
|
| 657 |
|
| 658 |
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
|
| 659 |
#define bmINFM bmBIT6
|
| 660 |
#define bmOEP bmBIT5
|
| 661 |
#define bmAUTOOUT bmBIT4
|
| 662 |
#define bmAUTOIN bmBIT3
|
| 663 |
#define bmZEROLENIN bmBIT2
|
| 664 |
// must be zero bmBIT1
|
| 665 |
#define bmWORDWIDE bmBIT0
|
| 666 |
|
| 667 |
/*
|
| 668 |
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
|
| 669 |
*/
|
| 670 |
#define bmNOAUTOARM bmBIT1 // these don't match the docs |
| 671 |
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs |
| 672 |
|
| 673 |
#define bmDYN_OUT bmBIT1 // these do... |
| 674 |
#define bmENH_PKT bmBIT0
|
| 675 |
|
| 676 |
|
| 677 |
/* Fifo Reset bits (FIFORESET) */
|
| 678 |
#define bmNAKALL bmBIT7
|
| 679 |
|
| 680 |
/* Endpoint Configuration (EPxCFG) */
|
| 681 |
#define bmVALID bmBIT7
|
| 682 |
#define bmIN bmBIT6
|
| 683 |
#define bmTYPE1 bmBIT5
|
| 684 |
#define bmTYPE0 bmBIT4
|
| 685 |
#define bmISOCHRONOUS bmTYPE0
|
| 686 |
#define bmBULK bmTYPE1
|
| 687 |
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
|
| 688 |
#define bm1KBUF bmBIT3
|
| 689 |
#define bmBUF1 bmBIT1
|
| 690 |
#define bmBUF0 bmBIT0
|
| 691 |
#define bmQUADBUF 0 |
| 692 |
#define bmINVALIDBUF bmBUF0
|
| 693 |
#define bmDOUBLEBUF bmBUF1
|
| 694 |
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
|
| 695 |
|
| 696 |
/* OUTPKTEND */
|
| 697 |
#define bmSKIP bmBIT7 // low 4 bits specify which end point |
| 698 |
|
| 699 |
/* GPIFTRIG defs */
|
| 700 |
#define bmGPIF_IDLE bmBIT7 // status bit |
| 701 |
|
| 702 |
#define bmGPIF_EP2_START 0 |
| 703 |
#define bmGPIF_EP4_START 1 |
| 704 |
#define bmGPIF_EP6_START 2 |
| 705 |
#define bmGPIF_EP8_START 3 |
| 706 |
#define bmGPIF_READ bmBIT2
|
| 707 |
#define bmGPIF_WRITE 0 |
| 708 |
|
| 709 |
/* EXIF bits */
|
| 710 |
#define bmEXIF_USBINT bmBIT4
|
| 711 |
#define bmEXIF_I2CINT bmBIT5
|
| 712 |
#define bmEXIF_IE4 bmBIT6
|
| 713 |
#define bmEXIF_IE5 bmBIT7
|
| 714 |
|
| 715 |
|
| 716 |
#endif /* FX2REGS_H */ |