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#!/usr/bin/env python
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#
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# Copyright 2008,2009 Free Software Foundation, Inc.
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# 
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# This file is part of GNU Radio
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# 
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# GNU Radio is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either asversion 3, or (at your option)
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# any later version.
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# 
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# GNU Radio is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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# GNU General Public License for more details.
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# 
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# You should have received a copy of the GNU General Public License
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# along with GNU Radio; see the file COPYING.  If not, write to
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# the Free Software Foundation, Inc., 51 Franklin Street,
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# Boston, MA 02110-1301, USA.
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import sys
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from common import *
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########################################################################
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# Template for raw text data describing registers
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# name addr[bit range inclusive] default optional enums
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########################################################################
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REGS_DATA_TMPL="""\
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########################################################################
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## address 0
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########################################################################
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sdio_bidirectional      0[7]     0      input, io
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lsb_msb_first           0[6]     0      msb, lsb
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soft_reset              0[5]     0
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sleep_mode              0[4]     0
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power_down_mode         0[3]     0
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x_1r_2r_mode            0[2]     0      2r, 1r
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pll_lock_indicator      0[1]     0
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########################################################################
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## address 1
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########################################################################
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filter_interp_rate      1[6:7]   0      1x, 2x, 4x, 8x
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modulation_mode         1[4:5]   0      none, fs_2, fs_4, fs_8
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zero_stuff_mode         1[3]     0
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mix_mode                1[2]     1      complex, real
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modulation_form         1[1]     0      e_minus_jwt, e_plus_jwt
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data_clk_pll_lock_sel   1[0]     0      pll_lock, data_clk
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########################################################################
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## address 2
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########################################################################
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signed_input_data       2[7]     0      signed, unsigned
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two_port_mode           2[6]     0      two_port, one_port
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dataclk_driver_strength 2[5]     0      weak, strong
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dataclk_invert          2[4]     0
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oneportclk_invert       2[2]     0
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iqsel_invert            2[1]     0
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iq_first                2[0]     0      i_first, q_first
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########################################################################
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## address 3
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########################################################################
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data_rate_clock_output  3[7]     0      pll_lock, spi_sdo
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pll_divide_ratio        3[0:1]   0      div1, div2, div4, div8
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########################################################################
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## address 4
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########################################################################
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pll_state               4[7]     0      off, on
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auto_cp_control         4[6]     0      dis, enb
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pll_cp_control          4[0:2]   0      50ua=0, 100ua=1, 200ua=2, 400ua=3, 800ua=7
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########################################################################
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## address 5 and 9
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########################################################################
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idac_fine_gain_adjust   5[0:7]   0
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qdac_fine_gain_adjust   9[0:7]   0
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########################################################################
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## address 6 and A
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########################################################################
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idac_coarse_gain_adjust 6[0:3]   0
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qdac_coarse_gain_adjust A[0:3]   0
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########################################################################
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## address 7, 8 and B, C
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########################################################################
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idac_offset_adjust_msb  7[0:7]   0
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idac_offset_adjust_lsb  8[0:1]   0
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idac_ioffset_direction  8[7]     0     out_a, out_b
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qdac_offset_adjust_msb  B[0:7]   0
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qdac_offset_adjust_lsb  C[0:1]   0
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qdac_ioffset_direction  C[7]     0     out_a, out_b
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"""
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########################################################################
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# Header and Source templates below
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########################################################################
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HEADER_TEXT="""
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#import time
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/***********************************************************************
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 * This file was generated by $file on $time.strftime("%c")
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 **********************************************************************/
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\#ifndef INCLUDED_AD9777_REGS_HPP
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\#define INCLUDED_AD9777_REGS_HPP
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\#include <boost/cstdint.hpp>
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struct ad9777_regs_t{
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#for $reg in $regs
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    #if $reg.get_enums()
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    enum $(reg.get_name())_t{
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        #for $i, $enum in enumerate($reg.get_enums())
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        #set $end_comma = ',' if $i < len($reg.get_enums())-1 else ''
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        $(reg.get_name().upper())_$(enum[0].upper()) = $enum[1]$end_comma
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        #end for
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    } $reg.get_name();
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    #else
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    boost::$reg.get_stdint_type() $reg.get_name();
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    #end if
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#end for
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    ad9777_regs_t(void){
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#for $reg in $regs
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        $reg.get_name() = $reg.get_default();
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#end for
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    }
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    boost::uint8_t get_reg(boost::uint8_t addr){
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        boost::uint8_t reg = 0;
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        switch(addr){
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        #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
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        case $addr:
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            #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
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            reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
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            #end for
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            break;
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        #end for
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        }
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        return reg;
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    }
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    boost::uint16_t get_write_reg(boost::uint8_t addr){
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        return (boost::uint16_t(addr) << 8) | get_reg(addr);
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    }
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    boost::uint16_t get_read_reg(boost::uint8_t addr){
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        return (boost::uint16_t(addr) << 8) | (1 << 7);
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    }
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};
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\#endif /* INCLUDED_AD9777_REGS_HPP */
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"""
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if __name__ == '__main__':
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    regs = map(reg, parse_tmpl(REGS_DATA_TMPL).splitlines())
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    open(sys.argv[1], 'w').write(parse_tmpl(HEADER_TEXT, regs=regs, file=__file__))