Revision 64e01dbe
| b/usrp2/fifo/packet_router.v | ||
|---|---|---|
| 31 | 31 |
output [35:0] eth_out_data, output eth_out_valid, input eth_out_ready |
| 32 | 32 |
); |
| 33 | 33 |
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assign wb_err_o = 1'b0; // Unused for now |
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assign wb_rty_o = 1'b0; // Unused for now |
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always @(posedge wb_clk_i) |
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wb_ack_o <= wb_stb_i & ~wb_ack_o; |
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//////////////////////////////////////////////////////////////////// |
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// CPU interface to this packet router |
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//////////////////////////////////////////////////////////////////// |
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wire [35:0] cpu_inp_data; |
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wire cpu_inp_valid; |
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wire cpu_inp_ready; |
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wire [35:0] cpu_out_data; |
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wire cpu_out_valid; |
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wire cpu_out_ready; |
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| 48 |
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| 34 | 49 |
//which buffer: 0 = CPU read buffer, 1 = CPU write buffer |
| 35 | 50 |
wire which_buf = wb_adr_i[BUF_SIZE+2]; |
| 36 | 51 |
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| 37 | 52 |
//////////////////////////////////////////////////////////////////// |
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// status and controls |
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// status and control handshakes
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| 39 | 54 |
//////////////////////////////////////////////////////////////////// |
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wire eth_to_cpu_flag_ack = control[0]; |
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wire cpu_inp_hs_ctrl = control[0]; |
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wire cpu_out_hs_ctrl = control[1]; |
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wire [BUF_SIZE-1:0] cpu_out_line_count = control[BUF_SIZE-1+16:0+16]; |
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wire cpu_inp_hs_stat; |
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assign status[0] = cpu_inp_hs_stat; |
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wire [BUF_SIZE-1:0] cpu_inp_line_count; |
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assign status[BUF_SIZE-1+16:0+16] = cpu_inp_line_count; |
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| 41 | 64 |
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wire eth_to_cpu_flag_rdy;
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assign status[0] = eth_to_cpu_flag_rdy;
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wire cpu_out_hs_stat;
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assign status[1] = cpu_out_hs_stat;
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| 44 | 67 |
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| 45 | 68 |
//////////////////////////////////////////////////////////////////// |
| 46 | 69 |
// Ethernet input control |
| 47 | 70 |
//////////////////////////////////////////////////////////////////// |
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//TODO: just connect eth input to cpu input for now |
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assign cpu_inp_data = eth_inp_data; |
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assign cpu_inp_valid = eth_inp_valid; |
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assign eth_inp_ready = cpu_inp_ready; |
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| 48 | 75 |
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localparam ETH_TO_CPU_STATE_WAIT_SOF = 0; |
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localparam ETH_TO_CPU_STATE_WAIT_EOF = 1; |
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localparam ETH_TO_CPU_STATE_WAIT_ACK_HI = 2; |
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localparam ETH_TO_CPU_STATE_WAIT_ACK_LO = 3; |
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//////////////////////////////////////////////////////////////////// |
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// Ethernet output control |
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//////////////////////////////////////////////////////////////////// |
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//TODO: just connect eth output to cpu output for now |
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assign eth_out_data = cpu_out_data; |
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assign eth_out_valid = cpu_out_valid; |
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assign cpu_out_ready = eth_out_ready; |
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| 53 | 83 |
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reg [1:0] eth_to_cpu_state; |
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reg [BUF_SIZE-1:0] eth_to_cpu_addr; |
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wire [BUF_SIZE-1:0] eth_to_cpu_addr_next = eth_to_cpu_addr + 1'b1; |
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//////////////////////////////////////////////////////////////////// |
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// Interface CPU input interface to memory mapped wishbone |
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//////////////////////////////////////////////////////////////////// |
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localparam CPU_INP_STATE_WAIT_SOF = 0; |
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localparam CPU_INP_STATE_WAIT_EOF = 1; |
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localparam CPU_INP_STATE_WAIT_CTRL_HI = 2; |
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localparam CPU_INP_STATE_WAIT_CTRL_LO = 3; |
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reg [1:0] cpu_inp_state; |
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reg [BUF_SIZE-1:0] cpu_inp_addr; |
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assign cpu_inp_line_count = cpu_inp_addr; |
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wire [BUF_SIZE-1:0] cpu_inp_addr_next = cpu_inp_addr + 1'b1; |
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| 57 | 96 |
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wire eth_to_cpu_reading_input = (
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eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_SOF ||
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eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_EOF
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wire cpu_inp_reading = (
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cpu_inp_state == CPU_INP_STATE_WAIT_SOF ||
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cpu_inp_state == CPU_INP_STATE_WAIT_EOF
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| 61 | 100 |
)? 1'b1 : 1'b0; |
| 62 | 101 |
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wire eth_to_cpu_we = eth_to_cpu_reading_input; |
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assign eth_inp_ready = eth_to_cpu_reading_input; |
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assign eth_to_cpu_flag_rdy = (eth_to_cpu_state == ETH_TO_CPU_STATE_WAIT_ACK_HI)? 1'b1 : 1'b0; |
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assign wb_err_o = 1'b0; // Unused for now |
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assign wb_rty_o = 1'b0; // Unused for now |
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always @(posedge wb_clk_i) |
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wb_ack_o <= wb_stb_i & ~wb_ack_o; |
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wire cpu_inp_we = cpu_inp_reading; |
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assign cpu_inp_ready = cpu_inp_reading; |
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assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; |
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| 71 | 105 |
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RAMB16_S36_S36 eth_to_cpu_buff(
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//port A = wishbone memory mapped address space |
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.DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
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RAMB16_S36_S36 cpu_inp_buff(
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//port A = wishbone memory mapped address space (output only)
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.DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0),
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.ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i), |
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//port B = input from ethernet packets
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.DOB(),.ADDRB(eth_to_cpu_addr),.CLKB(stream_clk),.DIB(eth_inp_data),.DIPB(4'h0),
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.ENB(eth_to_cpu_we),.SSRB(0),.WEB(eth_to_cpu_we)
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//port B = packet router interface to CPU (input only)
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.DOB(),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(cpu_inp_data),.DIPB(4'h0),
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.ENB(cpu_inp_we),.SSRB(0),.WEB(cpu_inp_we)
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| 79 | 113 |
); |
| 80 | 114 |
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| 81 | 115 |
always @(posedge stream_clk) |
| 82 | 116 |
if(stream_rst) begin |
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eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF;
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eth_to_cpu_addr <= 0;
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cpu_inp_state <= CPU_INP_STATE_WAIT_SOF;
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cpu_inp_addr <= 0;
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end |
| 86 | 120 |
else begin |
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case(eth_to_cpu_state)
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ETH_TO_CPU_STATE_WAIT_SOF: begin
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if (eth_inp_ready & eth_inp_valid & (eth_inp_data[32] == 1'b1)) begin
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eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_EOF;
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eth_to_cpu_addr <= eth_to_cpu_addr_next;
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case(cpu_inp_state)
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CPU_INP_STATE_WAIT_SOF: begin
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if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[32] == 1'b1)) begin
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cpu_inp_state <= CPU_INP_STATE_WAIT_EOF;
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cpu_inp_addr <= cpu_inp_addr_next;
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end |
| 93 | 127 |
end |
| 94 | 128 |
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ETH_TO_CPU_STATE_WAIT_EOF: begin
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if (eth_inp_ready & eth_inp_valid & (eth_inp_data[33] == 1'b1)) begin
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eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_HI;
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CPU_INP_STATE_WAIT_EOF: begin
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if (cpu_inp_ready & cpu_inp_valid & (cpu_inp_data[33] == 1'b1)) begin
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cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_HI;
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end |
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if (eth_inp_ready & eth_inp_valid) begin
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eth_to_cpu_addr <= eth_to_cpu_addr_next;
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if (cpu_inp_ready & cpu_inp_valid) begin
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cpu_inp_addr <= cpu_inp_addr_next;
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| 101 | 135 |
end |
| 102 | 136 |
end |
| 103 | 137 |
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ETH_TO_CPU_STATE_WAIT_ACK_HI: begin
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if (eth_to_cpu_flag_ack == 1'b1) begin
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eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_ACK_LO;
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CPU_INP_STATE_WAIT_CTRL_HI: begin
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if (cpu_inp_hs_ctrl == 1'b1) begin
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cpu_inp_state <= CPU_INP_STATE_WAIT_CTRL_LO;
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end |
| 108 | 142 |
end |
| 109 | 143 |
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ETH_TO_CPU_STATE_WAIT_ACK_LO: begin
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if (eth_to_cpu_flag_ack == 0'b1) begin
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eth_to_cpu_state <= ETH_TO_CPU_STATE_WAIT_SOF;
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CPU_INP_STATE_WAIT_CTRL_LO: begin
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if (cpu_inp_hs_ctrl == 1'b0) begin
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cpu_inp_state <= CPU_INP_STATE_WAIT_SOF;
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end |
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cpu_inp_addr <= 0; //reset the address counter |
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| 114 | 149 |
end |
| 115 | 150 |
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endcase //eth_to_cpu_state
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endcase //cpu_inp_state
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end |
| 118 | 153 |
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//////////////////////////////////////////////////////////////////// |
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// Interface CPU output interface to memory mapped wishbone |
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//////////////////////////////////////////////////////////////////// |
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localparam CPU_OUT_STATE_WAIT_CTRL_HI = 0; |
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localparam CPU_OUT_STATE_WAIT_CTRL_LO = 1; |
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localparam CPU_OUT_STATE_UNLOAD = 2; |
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reg [1:0] cpu_out_state; |
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reg [BUF_SIZE-1:0] cpu_out_addr; |
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wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1; |
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reg [BUF_SIZE-1:0] cpu_out_line_count_reg; |
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reg cpu_out_flag_sof; |
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reg cpu_out_flag_eof; |
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assign cpu_out_data[35:32] = {2'b0, cpu_out_flag_eof, cpu_out_flag_sof};
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assign cpu_out_valid = (cpu_out_state == CPU_OUT_STATE_UNLOAD)? 1'b1 : 1'b0; |
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assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0; |
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RAMB16_S36_S36 cpu_out_buff( |
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//port A = wishbone memory mapped address space (input only) |
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.DOA(),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), |
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.ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i), |
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//port B = packet router interface from CPU (output only) |
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.DOB(cpu_out_data[31:0]),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0), |
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.ENB(1'b1),.SSRB(0),.WEB(1'b0) |
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); |
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always @(posedge stream_clk) |
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if(stream_rst) begin |
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cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; |
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cpu_out_addr <= 0; |
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end |
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else begin |
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case(cpu_out_state) |
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CPU_OUT_STATE_WAIT_CTRL_HI: begin |
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if (cpu_out_hs_ctrl == 1'b1) begin |
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cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_LO; |
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end |
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cpu_out_line_count_reg <= cpu_out_line_count; |
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cpu_out_addr <= 0; //reset the address counter |
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end |
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|
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CPU_OUT_STATE_WAIT_CTRL_LO: begin |
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if (cpu_out_hs_ctrl == 1'b0) begin |
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cpu_out_state <= CPU_OUT_STATE_UNLOAD; |
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cpu_out_addr <= cpu_out_addr_next; |
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end |
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cpu_out_flag_sof <= 1'b1; |
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cpu_out_flag_eof <= 1'b0; |
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end |
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|
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CPU_OUT_STATE_UNLOAD: begin |
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if (cpu_out_ready & cpu_out_valid) begin |
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cpu_out_addr <= cpu_out_addr_next; |
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cpu_out_flag_sof <= 1'b0; |
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if (cpu_out_addr == cpu_out_line_count_reg) begin |
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cpu_out_flag_eof <= 1'b1; |
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end |
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else begin |
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cpu_out_flag_eof <= 1'b0; |
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end |
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if (cpu_out_flag_eof) begin |
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cpu_out_state <= CPU_OUT_STATE_WAIT_CTRL_HI; |
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end |
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end |
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end |
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endcase //cpu_out_state |
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end |
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| 119 | 225 |
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| 120 | 226 |
endmodule // packet_router |
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