root / host / lib / ic_reg_maps / gen_ad9522_regs.py @ 33393776
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#!/usr/bin/env python
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#
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# Copyright 2010 Ettus Research LLC
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#
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# This program is free software: you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation, either version 3 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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########################################################################
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# Template for raw text data describing registers
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# name addr[bit range inclusive] default optional enums
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########################################################################
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REGS_TMPL="""\
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sdo_active 0x000[7] 0
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lsb_first_addr_incr 0x000[6] 0
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soft_reset 0x000[5] 0
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mirror 0x000[3:0] 0
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readback_active_registers 0x004[0] 0
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pfd_polarity 0x010[7] 0
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cp_current 0x010[6:4] 7
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cp_mode 0x010[3:2] 3
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pll_power_down 0x010[1:0] 1
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r_counter_lsb 0x011[7:0] 1
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r_counter_msb 0x012[5:0] 0
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a_counter 0x013[5:0] 0
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b_counter_lsb 0x014[7:0] 3
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b_counter_msb 0x015[4:0] 0
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set_cp_pin_to_vcp_2 0x016[7] 0
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reset_r_counter 0x016[6] 0
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reset_a_and_b_counters 0x016[5] 0
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reset_all_counters 0x016[4] 0
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b_counter_bypass 0x016[3] 0
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prescaler_p 0x016[2:0] 6
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status_pin_control 0x017[7:2] 0
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antibacklash_pulse_width 0x017[1:0] 0
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enb_cmos_ref_input_dc_off 0x018[7] 0
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lock_detect_counter 0x018[6:5] 0
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digital_lock_detect_window 0x018[4] 0
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disable_digital_lock_detect 0x018[3] 0
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vco_calibration_divider 0x018[2:1] 3
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vco_calibration_now 0x018[0] 0
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r_a_b_counters_sync_pin_rst 0x019[7:6] 0
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r_path_delay 0x019[5:3] 0
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n_path_delay 0x019[2:0] 0
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enable_status_pin_divider 0x01A[7] 0
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ref_freq_monitor_threshold 0x01A[6] 0
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ld_pin_control 0x01A[5:0] 0
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enable_vco_freq_monitor 0x01B[7] 0
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enable_ref2_freq_monitor 0x01B[6] 0
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enable_ref1_freq_monitor 0x01B[5] 0
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refmon_pin_control 0x01B[4:0] 0
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disable_switchover_deglitch 0x01C[7] 0
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select_ref2 0x01C[6] 0
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use_ref_sel_pin 0x01C[5] 0
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enb_auto_ref_switchover 0x01C[4] 0
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stay_on_ref2 0x01C[3] 0
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enable_ref2 0x01C[2] 0
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enable_ref1 0x01C[1] 0
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enable_differential_ref 0x01C[0] 0
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enb_stat_eeprom_at_stat_pin 0x01D[7] 1
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enable_xtal_osc 0x01D[6] 0
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enable_clock_doubler 0x01D[5] 0
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disable_pll_status_reg 0x01D[4] 0
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enable_ld_pin_comparator 0x01D[3] 0
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enable_external_holdover 0x01D[1] 0
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enable_holdover 0x01D[0] 0
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external_zero_delay_fcds 0x01E[4:3] 0
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enable_external_zero_delay 0x01E[2] 0
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enable_zero_delay 0x01E[1] 0
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########################################################################
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#for $i in range(12)
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#set $addr = ($i + 0x0F0)
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out$(i)_format $(addr)[7] 0
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out$(i)_cmos_configuration $(addr)[6:5] 3
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out$(i)_polarity $(addr)[4:3] 0
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out$(i)_lvds_diff_voltage $(addr)[2:1] 1
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out$(i)_lvds_power_down $(addr)[0] 0
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#end for
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########################################################################
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#for $i in reversed(range(8))
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csdld_en_out_$i 0x0FC[$i] 0
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#end for
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########################################################################
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#for $i in reversed(range(4))
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csdld_en_out_$(8 + $i) 0x0FD[$i] 0
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#end for
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########################################################################
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#set $default_val = 0x7
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#for $i in range(4)
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#set $addr0 = hex($i*3 + 0x190)
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#set $addr1 = hex($i*3 + 0x191)
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#set $addr2 = hex($i*3 + 0x192)
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divider$(i)_low_cycles $(addr0)[7:4] $default_val
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divider$(i)_high_cycles $(addr0)[3:0] $default_val
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divider$(i)_bypass $(addr1)[7] 0
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divider$(i)_ignore_sync $(addr1)[6] 0
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divider$(i)_force_high $(addr1)[5] 0
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divider$(i)_start_high $(addr1)[4] 0
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divider$(i)_phase_offset $(addr1)[3:0] 0
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channel$(i)_power_down $(addr2)[2] 0
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disable_divider$(i)_ddc $(addr2)[0] 0
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#set $default_val /= 2
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#end for
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########################################################################
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vco_divider 0x1E0[2:0] 2
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power_down_clock_input_sel 0x1E1[4] 0
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power_down_vco_clock_ifc 0x1E1[3] 0
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power_down_vco_and_clock 0x1E1[2] 0
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select_vco_or_clock 0x1E1[1] 0
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bypass_vco_divider 0x1E1[0] 0
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disable_power_on_sync 0x230[3] 0
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power_down_sync 0x230[2] 0
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power_down_dist_ref 0x230[1] 0
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soft_sync 0x230[0] 0
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io_update 0x232[0] 0
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soft_eeprom 0xB02[1] 0
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enable_eeprom_write 0xB02[0] 0
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reg2eeprom 0xB03[0] 0
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"""
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########################################################################
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# Template for methods in the body of the struct
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########################################################################
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BODY_TMPL="""\
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boost::uint8_t get_reg(boost::uint16_t addr){
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boost::uint8_t reg = 0;
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switch(addr){
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#for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
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case $addr:
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#for $reg in filter(lambda r: r.get_addr() == addr, $regs)
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reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
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#end for
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break;
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#end for
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}
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return reg;
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}
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void set_reg(boost::uint8_t addr, boost::uint32_t reg){
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switch(addr){
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#for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
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case $addr:
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#for $reg in filter(lambda r: r.get_addr() == addr, $regs)
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$reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
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#end for
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break;
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#end for
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}
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}
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boost::uint32_t get_write_reg(boost::uint16_t addr){
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return (boost::uint32_t(addr) << 8) | get_reg(addr);
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}
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boost::uint32_t get_read_reg(boost::uint16_t addr){
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return (boost::uint32_t(addr) << 8) | (1 << 23);
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}
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"""
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if __name__ == '__main__': |
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import common; common.generate( |
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name='ad9522_regs',
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regs_tmpl=REGS_TMPL, |
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body_tmpl=BODY_TMPL, |
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file=__file__, |
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) |