root / host / lib / ic_reg_maps / gen_ad9522_regs.py @ 33393776
History | View | Annotate | Download (7.56 KB)
| 1 | 33393776 | Josh Blum | #!/usr/bin/env python
|
|---|---|---|---|
| 2 | #
|
||
| 3 | # Copyright 2010 Ettus Research LLC
|
||
| 4 | #
|
||
| 5 | # This program is free software: you can redistribute it and/or modify
|
||
| 6 | # it under the terms of the GNU General Public License as published by
|
||
| 7 | # the Free Software Foundation, either version 3 of the License, or
|
||
| 8 | # (at your option) any later version.
|
||
| 9 | #
|
||
| 10 | # This program is distributed in the hope that it will be useful,
|
||
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
| 13 | # GNU General Public License for more details.
|
||
| 14 | #
|
||
| 15 | # You should have received a copy of the GNU General Public License
|
||
| 16 | # along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||
| 17 | #
|
||
| 18 | |||
| 19 | ########################################################################
|
||
| 20 | # Template for raw text data describing registers
|
||
| 21 | # name addr[bit range inclusive] default optional enums
|
||
| 22 | ########################################################################
|
||
| 23 | REGS_TMPL="""\
|
||
| 24 | sdo_active 0x000[7] 0
|
||
| 25 | lsb_first_addr_incr 0x000[6] 0
|
||
| 26 | soft_reset 0x000[5] 0
|
||
| 27 | mirror 0x000[3:0] 0
|
||
| 28 | readback_active_registers 0x004[0] 0
|
||
| 29 | pfd_polarity 0x010[7] 0
|
||
| 30 | cp_current 0x010[6:4] 7
|
||
| 31 | cp_mode 0x010[3:2] 3
|
||
| 32 | pll_power_down 0x010[1:0] 1
|
||
| 33 | r_counter_lsb 0x011[7:0] 1
|
||
| 34 | r_counter_msb 0x012[5:0] 0
|
||
| 35 | a_counter 0x013[5:0] 0
|
||
| 36 | b_counter_lsb 0x014[7:0] 3
|
||
| 37 | b_counter_msb 0x015[4:0] 0
|
||
| 38 | set_cp_pin_to_vcp_2 0x016[7] 0
|
||
| 39 | reset_r_counter 0x016[6] 0
|
||
| 40 | reset_a_and_b_counters 0x016[5] 0
|
||
| 41 | reset_all_counters 0x016[4] 0
|
||
| 42 | b_counter_bypass 0x016[3] 0
|
||
| 43 | prescaler_p 0x016[2:0] 6
|
||
| 44 | status_pin_control 0x017[7:2] 0
|
||
| 45 | antibacklash_pulse_width 0x017[1:0] 0
|
||
| 46 | enb_cmos_ref_input_dc_off 0x018[7] 0
|
||
| 47 | lock_detect_counter 0x018[6:5] 0
|
||
| 48 | digital_lock_detect_window 0x018[4] 0
|
||
| 49 | disable_digital_lock_detect 0x018[3] 0
|
||
| 50 | vco_calibration_divider 0x018[2:1] 3
|
||
| 51 | vco_calibration_now 0x018[0] 0
|
||
| 52 | r_a_b_counters_sync_pin_rst 0x019[7:6] 0
|
||
| 53 | r_path_delay 0x019[5:3] 0
|
||
| 54 | n_path_delay 0x019[2:0] 0
|
||
| 55 | enable_status_pin_divider 0x01A[7] 0
|
||
| 56 | ref_freq_monitor_threshold 0x01A[6] 0
|
||
| 57 | ld_pin_control 0x01A[5:0] 0
|
||
| 58 | enable_vco_freq_monitor 0x01B[7] 0
|
||
| 59 | enable_ref2_freq_monitor 0x01B[6] 0
|
||
| 60 | enable_ref1_freq_monitor 0x01B[5] 0
|
||
| 61 | refmon_pin_control 0x01B[4:0] 0
|
||
| 62 | disable_switchover_deglitch 0x01C[7] 0
|
||
| 63 | select_ref2 0x01C[6] 0
|
||
| 64 | use_ref_sel_pin 0x01C[5] 0
|
||
| 65 | enb_auto_ref_switchover 0x01C[4] 0
|
||
| 66 | stay_on_ref2 0x01C[3] 0
|
||
| 67 | enable_ref2 0x01C[2] 0
|
||
| 68 | enable_ref1 0x01C[1] 0
|
||
| 69 | enable_differential_ref 0x01C[0] 0
|
||
| 70 | enb_stat_eeprom_at_stat_pin 0x01D[7] 1
|
||
| 71 | enable_xtal_osc 0x01D[6] 0
|
||
| 72 | enable_clock_doubler 0x01D[5] 0
|
||
| 73 | disable_pll_status_reg 0x01D[4] 0
|
||
| 74 | enable_ld_pin_comparator 0x01D[3] 0
|
||
| 75 | enable_external_holdover 0x01D[1] 0
|
||
| 76 | enable_holdover 0x01D[0] 0
|
||
| 77 | external_zero_delay_fcds 0x01E[4:3] 0
|
||
| 78 | enable_external_zero_delay 0x01E[2] 0
|
||
| 79 | enable_zero_delay 0x01E[1] 0
|
||
| 80 | ########################################################################
|
||
| 81 | #for $i in range(12)
|
||
| 82 | #set $addr = ($i + 0x0F0)
|
||
| 83 | out$(i)_format $(addr)[7] 0
|
||
| 84 | out$(i)_cmos_configuration $(addr)[6:5] 3
|
||
| 85 | out$(i)_polarity $(addr)[4:3] 0
|
||
| 86 | out$(i)_lvds_diff_voltage $(addr)[2:1] 1
|
||
| 87 | out$(i)_lvds_power_down $(addr)[0] 0
|
||
| 88 | #end for
|
||
| 89 | ########################################################################
|
||
| 90 | #for $i in reversed(range(8))
|
||
| 91 | csdld_en_out_$i 0x0FC[$i] 0
|
||
| 92 | #end for
|
||
| 93 | ########################################################################
|
||
| 94 | #for $i in reversed(range(4))
|
||
| 95 | csdld_en_out_$(8 + $i) 0x0FD[$i] 0
|
||
| 96 | #end for
|
||
| 97 | ########################################################################
|
||
| 98 | #set $default_val = 0x7
|
||
| 99 | #for $i in range(4)
|
||
| 100 | #set $addr0 = hex($i*3 + 0x190)
|
||
| 101 | #set $addr1 = hex($i*3 + 0x191)
|
||
| 102 | #set $addr2 = hex($i*3 + 0x192)
|
||
| 103 | divider$(i)_low_cycles $(addr0)[7:4] $default_val
|
||
| 104 | divider$(i)_high_cycles $(addr0)[3:0] $default_val
|
||
| 105 | divider$(i)_bypass $(addr1)[7] 0
|
||
| 106 | divider$(i)_ignore_sync $(addr1)[6] 0
|
||
| 107 | divider$(i)_force_high $(addr1)[5] 0
|
||
| 108 | divider$(i)_start_high $(addr1)[4] 0
|
||
| 109 | divider$(i)_phase_offset $(addr1)[3:0] 0
|
||
| 110 | channel$(i)_power_down $(addr2)[2] 0
|
||
| 111 | disable_divider$(i)_ddc $(addr2)[0] 0
|
||
| 112 | #set $default_val /= 2
|
||
| 113 | #end for
|
||
| 114 | ########################################################################
|
||
| 115 | vco_divider 0x1E0[2:0] 2
|
||
| 116 | power_down_clock_input_sel 0x1E1[4] 0
|
||
| 117 | power_down_vco_clock_ifc 0x1E1[3] 0
|
||
| 118 | power_down_vco_and_clock 0x1E1[2] 0
|
||
| 119 | select_vco_or_clock 0x1E1[1] 0
|
||
| 120 | bypass_vco_divider 0x1E1[0] 0
|
||
| 121 | disable_power_on_sync 0x230[3] 0
|
||
| 122 | power_down_sync 0x230[2] 0
|
||
| 123 | power_down_dist_ref 0x230[1] 0
|
||
| 124 | soft_sync 0x230[0] 0
|
||
| 125 | io_update 0x232[0] 0
|
||
| 126 | soft_eeprom 0xB02[1] 0
|
||
| 127 | enable_eeprom_write 0xB02[0] 0
|
||
| 128 | reg2eeprom 0xB03[0] 0
|
||
| 129 | """
|
||
| 130 | |||
| 131 | ########################################################################
|
||
| 132 | # Template for methods in the body of the struct
|
||
| 133 | ########################################################################
|
||
| 134 | BODY_TMPL="""\
|
||
| 135 | boost::uint8_t get_reg(boost::uint16_t addr){
|
||
| 136 | boost::uint8_t reg = 0;
|
||
| 137 | switch(addr){
|
||
| 138 | #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
|
||
| 139 | case $addr:
|
||
| 140 | #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
|
||
| 141 | reg |= (boost::uint8_t($reg.get_name()) & $reg.get_mask()) << $reg.get_shift();
|
||
| 142 | #end for
|
||
| 143 | break;
|
||
| 144 | #end for
|
||
| 145 | }
|
||
| 146 | return reg;
|
||
| 147 | }
|
||
| 148 |
|
||
| 149 | void set_reg(boost::uint8_t addr, boost::uint32_t reg){
|
||
| 150 | switch(addr){
|
||
| 151 | #for $addr in sorted(set(map(lambda r: r.get_addr(), $regs)))
|
||
| 152 | case $addr:
|
||
| 153 | #for $reg in filter(lambda r: r.get_addr() == addr, $regs)
|
||
| 154 | $reg.get_name() = $(reg.get_type())((reg >> $reg.get_shift()) & $reg.get_mask());
|
||
| 155 | #end for
|
||
| 156 | break;
|
||
| 157 | #end for
|
||
| 158 | }
|
||
| 159 | }
|
||
| 160 |
|
||
| 161 | boost::uint32_t get_write_reg(boost::uint16_t addr){
|
||
| 162 | return (boost::uint32_t(addr) << 8) | get_reg(addr);
|
||
| 163 | }
|
||
| 164 |
|
||
| 165 | boost::uint32_t get_read_reg(boost::uint16_t addr){
|
||
| 166 | return (boost::uint32_t(addr) << 8) | (1 << 23);
|
||
| 167 | }
|
||
| 168 |
|
||
| 169 | """
|
||
| 170 | |||
| 171 | if __name__ == '__main__': |
||
| 172 | import common; common.generate( |
||
| 173 | name='ad9522_regs',
|
||
| 174 | regs_tmpl=REGS_TMPL, |
||
| 175 | body_tmpl=BODY_TMPL, |
||
| 176 | file=__file__, |
||
| 177 | ) |