Revision 27eb894c usrp2/top/u1e/u1e_core.v

b/usrp2/top/u1e/u1e_core.v
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   // GPMC
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   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
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   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
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   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,
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   input EM_NWE, input EM_NOE,
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   inout db_sda, inout db_scl,
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   output sclk, output [7:0] sen, output mosi, input miso,
......
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   assign debug_clk = { EM_CLK, clk_fpga };


  		




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   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun },


  		




  
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   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },


  		




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		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },


  		




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		    { EM_D } };


  		




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