Revision 27eb894c

b/usrp2/top/u1e/u1e.ucf
32 32 
NET "EM_A<1>"  LOC = "C15"  ;
33 33 

  		




  34
  34
  
    
NET "EM_NCS6"  LOC = "E17"  ;


  		




  35
  
  
    
#NET "EM_NCS5"  LOC = "E10"  ;


  		




  
  35
  
    
NET "EM_NCS5"  LOC = "E10"  ;


  		




  36
  36
  
    
NET "EM_NCS4"  LOC = "E6"  ;


  		




  37
  37
  
    
#NET "EM_NCS1"  LOC = "D18"  ;


  		




  38
  38
  
    
#NET "EM_NCS0"  LOC = "D17"  ;


  		












  

    
      b/usrp2/top/u1e/u1e.v
    
  





  8
  8
  
    

  		




  9
  9
  
    
   // GPMC


  		




  10
  10
  
    
   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,


  		




  11
  
  
    
   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,


  		




  
  11
  
    
   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,


  		




  
  12
  
    
   input EM_NWE, input EM_NOE,


  		




  12
  13
  
    

  		




  13
  14
  
    
   inout db_sda, inout db_scl, // I2C


  		




  14
  15
  
    

  		




  ......




  116
  117
  
    
		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),


  		




  117
  118
  
    
		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),


  		




  118
  119
  
    
		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),


  		




  119
  
  
    
		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 


  		




  120
  
  
    
		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),


  		




  
  120
  
    
		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS5(EM_NCS5), 


  		




  
  121
  
    
		     .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE),


  		




  121
  122
  
    
		     .db_sda(db_sda), .db_scl(db_scl),


  		




  122
  123
  
    
		     .sclk(sclk), .sen({cgen_sen_b,sen_codec,db_sen_tx,db_sen_rx}), .mosi(mosi), .miso(miso),


  		




  123
  124
  
    
		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 


  		












  

    
      b/usrp2/top/u1e/u1e_core.v
    
  





  11
  11
  
    
   


  		




  12
  12
  
    
   // GPMC


  		




  13
  13
  
    
   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,


  		




  14
  
  
    
   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,


  		




  
  14
  
    
   input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6,


  		




  
  15
  
    
   input EM_NWE, input EM_NOE,


  		




  15
  16
  
    
   


  		




  16
  17
  
    
   inout db_sda, inout db_scl,


  		




  17
  18
  
    
   output sclk, output [7:0] sen, output mosi, input miso,


  		




  ......




  439
  440
  
    

  		




  440
  441
  
    
   assign debug_clk = { EM_CLK, clk_fpga };


  		




  441
  442
  
    

  		




  442
  
  
    
   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, rx_overrun, tx_underrun },


  		




  
  443
  
    
   assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },


  		




  443
  444
  
    
		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },


  		




  444
  445
  
    
		    { EM_D } };


  		




  445
  446
  
    

  		












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