Activity
From 01/28/2012 to 03/27/2012
03/27/2012
- 10:05 pm Revision 298d0ae5: examples: Transport Hammer - a stress test that calls for random or user-speci...
- 07:56 pm Revision 3f79cb0c: fpga: extract usage summary from map file
- 12:54 am Revision 40884c94: Merge branch 'master' into next
- 12:53 am Revision 74a9352c: Merge branch 'maint'
- 12:51 am Revision 097f20df: dbsrx: limit the USRP1 + DBSRX GPIO clock rate to 4MHz
- This fixes the lockup/clocking condition when the following hw combo is used:
USRP1 r4.5 + DBSRX + another i2c board - 12:51 am Revision 277d4d2f: usrp2: possible fix for invalid broadcast replies
03/26/2012
- 11:46 pm Revision 94872763: Merge branch 'maint'
- 10:11 pm Revision 95de4f73: Merge branch 'fpga_maint' into maint
- 10:09 pm Revision a40bb6e9: Merge branch 'master' into next
- 09:30 pm Revision c6fd517a: fx2: simplify i2c code and overload eeprom read/write
- Overload eeprom routines to do it in 1 transaction,
since default will split it up into many for each byte. - 07:23 pm Revision 842c54ec: B100: port cleanups from b100-txbug to this branch
- 05:25 pm Revision d966b217: Merge branch 'maint'
- 05:20 pm Revision 68510d56: uhd: use release mode and git count for stable and unstable builds
03/25/2012
- 08:23 pm Revision 6d2d62ca: fpga: fifo_2clock handles widths and sizes in-between corgens
- 07:46 pm Revision fe6c37c4: b100: cleanup redundant logic for slwr and slrd
- 08:17 am Revision fb8e1195: b100: extra data pktend cycle for fifo addr
- 04:20 am Revision 42a52c06: b100: slave fifo fix for dst/src ready signals
- Some of the changes my be overkill,
but the idea is to be more careful about
allowing FIFO IO to occur on transitions...
03/23/2012
- 11:43 pm Revision ef3deabe: Merge branch 'master' into next
- 11:42 pm Revision 793c8c00: Merge branch 'maint'
- 11:31 pm Revision 17068bc3: Changes preinst.in to 'echo' instead of 'ls'
- 11:07 pm Revision ae1ebd8a: uhd: updated sync docs for timed commands
- 09:41 pm Revision 672da0df: Merge branch 'fpga_next' into next
- 09:37 pm Revision 6acafe3a: Merge branch 'master' into next
- 09:37 pm Revision 7e395dab: Merge branch 'maint'
- 09:36 pm Revision 05a9c610: sbx: mods for PLL sync reset
- 09:36 pm Revision 035c1b39: sbx: various fixes and tweaks for locking
- 09:36 pm Revision 40576b23: sbx: no readback during tuning, cache lock detect status when read
- 09:36 pm Revision 6d649391: fifo ctrl: code reorganization and integer wrap-around arithmetic
- 09:36 pm Revision 6ff4100f: fifo ctrl: implement timed command feature detection
- 09:36 pm Revision cda81f58: usrp2: added vrt pack/unpacker to fifo ctrl
- 09:36 pm Revision ea659bd8: fifo ctrl: use regular iface for U2_REG_MISC_CTRL_CLOCK
- 09:36 pm Revision f3f64abc: fifo ctrl: various tweaks
- 09:36 pm Revision 672a7776: fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no blinkie
- 09:36 pm Revision 12223186: fifo ctrl: spi core work and host implementation
- 09:36 pm Revision 08e2432c: spi: work on fw support for simple spi core
- 09:36 pm Revision ee04c245: usrp2: permanent timeout increase for timed commands
- 09:36 pm Revision b1d82758: usrp2: implementation of timed commands working
- 09:36 pm Revision f59ef44a: usrp2: integrated fifo ctrl into usrp2 modules, implemented window'd acking
- 09:36 pm Revision d7a35346: uhd: added setup sleep to tx waveforms
- 09:36 pm Revision fe0a5162: usrp2: host and fw implementation for fifo control
- 09:36 pm Revision e4d3f63c: usrp2: work on alternative stream destination
- 07:14 pm Revision b60fccc5: usrp: fix for rx_frontend_core_200 dc offset
- Mask off upper bits when setting a constant offset (I and Q regs).
The sign bits (if negative) can flow off into the ...
03/22/2012
03/21/2012
- 06:37 pm Revision d97b9dee: docs: whitespace fixing usrp2 docs
- 06:36 pm Revision e69bcd3e: uhd: add calls to query an ABI compat string
- 06:31 pm Revision b22c32bd: usrp2: fw unlocks when ICMP dest unreachable
03/19/2012
03/16/2012
- 09:02 pm Revision 7e296167: Disabling the SBX mixer and baseband amp causes grief
- Some ADA4927 / AD5380 combinations do not appreciate
being disabled, so lets not disable them - 08:59 pm Revision 6d53b7eb: tx_bursts: set EOB on nsamps <= spb
- 08:11 pm Revision b5385fa7: docs: Just added a couple of clarifying notes to the N2Xx docs.
- 06:29 pm Revision fdf98d12: fifo ctrl: minor fixes for spi core, swap time define
- 06:29 pm Revision 28e0a0e3: fifo ctrl: parameterize having a proto header
- 06:29 pm Revision 56f37de8: fifo ctrl: rename fifo ctrl module and add sid ack param
- 06:29 pm Revision 6d70e5b3: spi core: ready logic low one cycle earlier
- FIFO ctrl can poke registers every other cycle,
the extra time to register not ready for spi core was too long.
And i... - 06:29 pm Revision f031d377: fifo ctrl: simplified perfs, added spi clock idle phase
- 06:29 pm Revision 9f1c107b: fifo ctrl: minor fixes from last commit
- 06:29 pm Revision c7adcbe4: fifo ctrl: spi core work, fifo ctrl perifs, usrp2 support
- Continued work on simple spi core.
Added peripherals input to fifo ctrl so perifs can backpressure fifo ctrl.
Copie... - 06:29 pm Revision 63e71a29: fifo_ctrl: switched to medfifo and separate result fifo
- 06:29 pm Revision 06654cac: fifo ctrl: simplified result packets (no tsf or sid)
- 06:29 pm Revision 46c612ea: spi: created simple spi core (sr based)
- 06:29 pm Revision 0d712ac8: fifo_ctrl: clear settings reg, and flow control
- 06:29 pm Revision d6da6c41: fifo ctrl: added time compare for timed commands
- 06:29 pm Revision 74ceca35: srb: created command queue, in and out state machines
- 06:29 pm Revision 78b9db58: usrp2: first pass implementation of fifo control
- 06:29 pm Revision 54e09f39: usrp2: added vrt pack/unpacker to fifo ctrl
- 06:27 pm Revision 63991f79: B100: enable_gpif(0) disables FIFO output clock on FX2. this prevents the "stu...
- 04:04 pm Revision f91e247d: usrp: fix from "rev iq correction"
- Must zero out the default IQ correction to have zero effect by default.
03/15/2012
03/14/2012
- 05:41 pm Revision 462b27e7: uhd: make atlbase options for msvc build
- 07:02 am Revision 8a33423a: uhd: rev iq correction numbers format
- 12:31 am Revision abab58f5: Add a toolchain file to build cross using e100 toolchain.
- This appears to build uhd cross using my toolchain. Run cmake with:
cmake -DCMAKE_TOOLCHAIN_FILE=../cmake/Toolchains... - 12:26 am Revision 927cf239: For Windows installers, CMake checks the size of void* to differentiate betwee...
03/13/2012
03/12/2012
- 08:54 pm Revision 7a95ea36: fpga: force -include_global for custom sources
- ISE will not recognize custom sources as part of the hierarchy,
and thus will not compile (unless its the first macro... - 07:10 pm Revision 6ba4e816: usrp: fix wildcard set for time/clock source
03/11/2012
- 10:56 pm Revision 72d78c6f: uhd: added fullscale option stream arg
- 10:54 pm Revision b2c0d1f5: Make DBSRX* set default bandwidth based on codec rate
- 10:53 pm Revision 715fd038: Fix RSSI measurement
- Improve incorrect calculation in XCVR
Remove RFX rssi sensor due to limited dynamic range giving strange
... - 09:06 pm Revision 38b138b3: Merge branch 'fpga_master'
03/09/2012
02/29/2012
- 10:26 pm Revision b61f4ad6: usrp1: fix for cordic init, cant do it that way on tx
- 06:01 pm Revision 757dd091: Changes Windows installer filename to match naming convention of Ubuntu and Fe...
- 05:52 pm Revision a58ee6e2: uhd: fix sc16 to sc8 conversion table
- 1) this was registered as the sc8 to sc16 converter,
probably messed that up as well
2) the cast to index was wrong,... - 05:31 pm Revision fedad063: usrp2: device locking tweaks
- 1) use bottom bit for force lock condition,
that way we never check the time after proper shutdown
2) dont allow loc...
02/28/2012
- 11:54 pm Revision 84567c20: Changing UHD to 'USRP HD' in one last place.
- 09:35 pm Revision bd7e53d3: usrp: reset cordics on init after tick rate update
- 09:31 pm Revision aa422ece: Changes images CMakeLists.txt to be consistent with new UHD version naming system
- 09:20 pm Revision dfaf1f93: uhd: fixed some compile warnings for msvc
- 06:36 pm Revision 2033713d: cmake:
- More git info used for build info
UHD version incorporates build info
apt/yum repos use new version number
New instal...
02/27/2012
- 11:40 pm Revision f591c4a8: uhd: fixed send pkt handler, vrt packet type was uninitialized
- This fixes a bug where the sc8 engine will not interpret
the packet as an IF data packet due to uninitialized bits.
I... - 07:37 pm Revision 12260e71: usrp2: removed unused memory map entries
02/25/2012
- 01:44 am Revision c8c8df3c: uhd: added fullscale option stream arg
- 12:56 am Revision a967cbd3: usrp2: work on alternative stream destination
02/24/2012
- 06:06 pm Revision 11e9429b: usrp1: fix to use the db connection type to determine DAC sign
- Unlike the other products, usrp1 uses the DAC and not DSP
to perform baseband frequency shifting in the hardware.
The...
02/22/2012
- 01:42 am Revision 1156d9b2: usrp1: fix advertised samples per packet in send streamer
- Must subtract off the 511 for 512 modulus remainder commit.
This bug was introduced by the conversion to streamer API.
02/21/2012
- 07:34 pm Revision 1c29b595: Try really hard to get cmake to use compiler flags from the toolchain file.
- See: http://www.mail-archive.com/cmake@cmake.org/msg33248.html
Also credit to OpenEmbedded for doing something simil... - 04:48 pm Revision f0ac072a: usb: added /opt/local to libusb search path
- For OSX from MLD
02/20/2012
- 11:33 pm Revision 2e85c4a2: usrp2: some tweaks to the device locking logic
- 08:52 pm Revision ad0562d8: Try really hard to get cmake to use compiler flags from the toolchain file.
- See: http://www.mail-archive.com/cmake@cmake.org/msg33248.html
Also credit OpenEmbedded for doing something similar ... - 06:51 pm Revision b1f34b4f: usrp2: added retry logic to control packets
02/19/2012
- 07:38 am Revision 0df49b75: usrp2: changed download url for dd.exe
- 06:21 am Revision f500b92e: Merge branch 'fpga_master'
- 06:15 am Revision e230fefb: usrp2/nseries: added churn to meet timing
- Added churn to readback mux on nseries to make n200r4 meet timing.
Also added churn to usrp2 for parallelism, but ass... - 12:46 am Revision 026f57d2: vita rx: trigger clear after packet tranfer
- To avoid blocking conditions down the pipe,
avoid clearing vita rx during packet transfer.
Adds state machine to del...
02/18/2012
- 10:40 pm Revision e9e670d7: uhd: added -fvisibility-inlines-hidden
- 02:18 am Revision 3ddbcb60: Merge branch 'next'
- 12:55 am Revision ace44890: Merge branch 'fpga_next' into next
- 12:55 am Revision 8f8ac339: dsp rework: fix for vita occ trailer packing
- 12:52 am Revision 2e37dd87: dsp rework: fix dspengine_8to16 to handle padded packets
02/17/2012
02/15/2012
- 11:57 pm Revision df9be31e: Merge branch 'master' into next
- 11:54 pm Revision 48c1df61: Merge branch 'fpga_next' into next
- 11:44 pm Revision 59d06f71: dsp rework: added flusher to vita tx chain on clear
- 11:44 pm Revision 831213bd: dsp rework: added flusher to vita tx chain on clear
- 02:26 am Revision 3060006b: uhd: added async md user payload and common utils
- 12:34 am Revision 82d38412: b100: use frame boundary to calculate frame size
02/14/2012
- 11:03 pm Revision 24d1afa3: Merge branch 'dsp_rework' into next
- 11:01 pm Revision 1463a78f: b100: reset/reenumerate fx2 for bad endpoint state
- Determine state of control endpoint,
re-enumerate to put in a known state,
rerun some initialization code. - 08:03 pm Revision 8bd255c5: b100: added transport flushes and moved around reset code
- 07:37 pm Revision 2f21932a: dsp rework: minor fix sph, set has time spec for tsf only
- 03:22 am Revision df946523: uhd: inline time spec accessors for minor improvement
02/13/2012
- 06:21 pm Revision 42e906a3: dsp rework: minor simplification in vita_tx_deframer
- all n-series devices meet timing
02/12/2012
- 11:02 pm Revision aa9dceed: Merge branch 'master' into next
- 11:01 pm Revision 070d1679: Merge branch 'fpga_next' into next
- 10:51 pm Revision 1fab7e9d: usrp1: big endian compile fix, conversion should cast to unsigned
- The htonx only takes unsigned integers, cast the int16 to uint16.
- 10:38 pm Revision 4a27f6e4: uhd: add over-the-wire option to tx waveforms
- 10:17 pm Revision bada7617: dsp rework: full-rate pipelining in vita tx deframer
- The vita tx deframer can now pass payload at clock rate.
This enables TX streaming at interpolations factors of 2.
T...
02/10/2012
- 08:13 pm Revision 6d45600a: dsp rework: pass enables into glue, update power trig, parameterize, fix modul...
- DSP enables now pass through the glue and custom modules so it can be user-controlled.
Updated power trigger to curr... - 03:02 am Revision 8442ea5e: b100/usrp1: various tweaks for compiler warns and valgrind
- 01:59 am Revision 11510003: uhd: various tweaks for compiler warns and valgrind
- 01:06 am Revision b6da2fe9: uhd: fixed sse2 conversion fc32 to sc8_item32_be
- 12:54 am Revision 4044a9ee: uhd: fixed orc conversion fc32 to sc8_item32_be
02/09/2012
- 10:31 pm Revision ae1ee33e: Merge branch 'fpga_next' into next
- 07:39 pm Revision 10a4d951: B100: Firmware reset tweaks.
- 07:01 am Revision cfba2388: uhd: added sse2 conversions for fc32 to sc8
- 03:22 am Revision d4668471: uhd: added sse2 conversions for fc64 to sc8
02/08/2012
- 10:24 pm Revision 122b9477: windows: do not set process wide priority from thread prio
- 09:50 pm Revision 52a10572: Add Orc functions to convert to sc8. bswap version is a bit of a hack.
- 09:12 pm Revision 9429905c: e100: loopback test fix after register tweaks
- 08:37 pm Revision 2a79f192: uhd: better quantization check for convert test
- 01:33 am Revision ec58790e: Fixing TX mixer disable, maxing out attenuation when not in use.
- 01:27 am Revision 9cc4c37f: Fixing ADF4351 dividers, even though they won't get used.
- 01:27 am Revision 1bef3487: Random formatting while reading through ATR.
02/07/2012
- 07:59 pm Revision 893af3dc: uhd: added sc8 conversion tests
- 12:46 am Revision 3af7fe85: Merge branch 'fpga_next' into next
- 12:40 am Revision 5eec31fa: dsp rework: implement 64 bit ticks, no seconds
- 12:40 am Revision 34db7474: dsp rework: implement 64 bit ticks no seconds
02/06/2012
- 09:02 pm Revision 947d0ffa: B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.
- 09:01 pm Revision 5c56ca57: B100: use FPGA external reset on init
02/05/2012
- 12:38 am Revision a9d30712: dsp rework: pass vita clears into dsp modules, unified fifo clears
- 12:38 am Revision c6e63c9d: b100/e100: unify rx/tx fifo clears into one
02/04/2012
- 11:12 pm Revision 1e3cb864: uhd: added/renamed various readme files
- 11:12 pm Revision 89ce89c9: b100: timing constraints on GPIF lines
- 10:35 pm Revision 04e9d23d: b100: delete some unused registers from map
- 04:41 pm Revision e0952709: b100: delete some unused registers from map
- 04:38 pm Revision fc8bab70: Merge branch 'fpga_next' into next
- 01:38 am Revision 0d2acffa: B100/B150: firmware disable FIFOs until host enables to keep junk out
- 01:37 am Revision a59763c5: B100/B150: timing on GPIF lines
02/03/2012
- 11:38 pm Revision 1b489be2: b100: connect all clears for gpif
- 06:57 pm Revision f88dd228: dsp rework: added otw mode for benchmark app
- 04:59 am Revision ae1997f8: power_trig: test code for power trigger
- 04:09 am Revision 97a8f455: dsp rework: move setting address of format register
- 04:08 am Revision e64b6e6c: dsp rework: rehash of the custom module stuff and readme
- 01:57 am Revision 1ce83a07: power_trig: first cut at power trigger with fixed delay
02/02/2012
- 11:15 pm Revision b7ff81c9: dsp rework: work on usb wrapper for smaller packets, large luts
- 07:00 pm Revision 17f5776c: dsp_rework: testbench enhancements
- 09:34 am Revision 95f8d2a3: uhd: updated sync docs for current API
- 02:02 am Revision 5e972e74: b100: sc8 mode not implemented error
- 02:02 am Revision 7e6a0855: dsp rework: custom engine module for rx/tx vita chain
- 12:35 am Revision 6bbcb202: dsp rework: register the sample in vita tx ctrl
02/01/2012
- 09:41 pm Revision 6525ddaf: Merge branch 'slave_fifo_rebase' into dsp_rework
- Conflicts:
usrp2/top/B100/u1plus_core.v - 06:05 pm Revision a0887f3b: b100: bump compat numbers for slave fifo mode
- Conflicts:
host/lib/usrp/b100/b100_impl.hpp - 06:05 pm Revision be14ffa8: B100: Modified TX send size to achieve 10.7Msps.
- 06:04 pm Revision 081714b4: B100 firmware changes to allow slave mode TX/RX.
- 06:04 pm Revision 81b4689c: B100 host code changes to remove TX padding, remove RX padding, increase max a...
- 05:48 pm Revision d27125b9: dsp rework: account for no sid used in tx vita pkt
- 05:47 pm Revision c4075163: dsp rework: paramaterize post_engine_buffering
- 01:22 am Revision 7b69532a: dsp_rework: handle longer headers
01/31/2012
- 10:56 pm Revision d46c176a: dsp rework: tx trailer, scaling work (peak)
- 10:56 pm Revision 781cafa8: gen2: added user setting regs api and user core
- 10:56 pm Revision aa95e53a: dsp rework: work on scaling and args parsing on RX and TX dsp
- This simplified some copy pasta in the io_impl.cpp files,
and adds a place for sc8 tx mode in the tx dsp core code. - 10:56 pm Revision 8f25550d: dsp rework: implemented new scalefactor in rx dsp core
- 10:56 pm Revision 72359ea1: uhd: implement convert_sc8to_sc16 table w/ scalar
- 10:44 pm Revision 5b06adb7: uhd: branch-less round for time spec convert to ticks
- This fixes valgrind warnings with branching on unit'd values,
and possible exceptions thrown on bad unit'd values.
A... - 08:06 pm Revision 08b60ada: dsp_rework: more thorough test
- 07:04 am Revision 531a7910: dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering
- 06:22 am Revision 327c2586: dsp rework: work on 8 to 16 engine (usrp2 ok)
- 12:35 am Revision 9803334f: dsp_engine: work with transport header
01/30/2012
- 11:09 pm Revision 05644d7d: dsp rework: integrated dspengine_8to16, some tweaks
- 07:09 am Revision ac35b413: dsp: 8 to 16 bit conversion for tx side. believed to be functional
01/29/2012
- 12:01 am Revision 724e4a9e: dsp rework: increase the number of effective bits in the duc scale factor
- This will be useful for effecting the dynamic range of the sc8 tx mode.
01/28/2012
- 10:26 pm Revision 15a717c0: dsp rework: added double buffer interface to vita tx
- 08:21 pm Revision 9f972999: dsp rework: moved scale and round into ddc chain
- 16to8 engine now performs only a clip from 16->8
- 05:19 am Revision 0ff51a35: dsp rework: top level fixes B100/E100
- 03:20 am Revision 4f94819a: dsp rework: integrated custom dsp module shells
- 03:09 am Revision e30cf4ec: usrp1/b100: reenumeration loop with timeout only when found
Also available in: Atom