fpga

vita: moved clear register to overlap with nchan register

This fixes the bug where setting the format clears the vita RX.
This is only an issue when the noclear option is set by UHD,
because the format register is always so, so it always clears.
Note: noclear is there to support the backwards compat API (pre streamer)....

b100: fix slave fifo data xfer exit condition

When exiting the read/write data state,
when the transfer count maxes out/peaks,
the fifo read/write signals were getting this
condition the cycle after with the state change.

B100: port cleanups from b100-txbug to this branch

b100: cleanup redundant logic for slwr and slrd

b100: slave fifo fix for dst/src ready signals

Some of the changes my be overkill,
but the idea is to be more careful about
allowing FIFO IO to occur on transitions.

The cal app was able to complete successfully.

fpga: fix custom defs in some top level makefiles

vita rx: trigger clear after packet tranfer

To avoid blocking conditions down the pipe,
avoid clearing vita rx during packet transfer.

Adds state machine to delay the clear until after xfer completes.

dsp_engine: fix for upper/lower swap, and odd length packets

dsp rework: minor simplification in vita_tx_deframer

all n-series devices meet timing

dsp rework: pass enables into glue, update power trig, parameterize, fix module inc

DSP enables now pass through the glue and custom modules so it can be user-controlled.

Updated power trigger to current spec, and added comments

Pass width from dsp into glue, and use width to parameterize wires...

B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.

b100: timing constraints on GPIF lines

power_trig: test code for power trigger

power_trig: first cut at power trigger with fixed delay

dsp rework: custom engine module for rx/tx vita chain

Merge branch 'slave_fifo_rebase' into dsp_rework

Conflicts:
usrp2/top/B100/u1plus_core.v

dsp_rework: handle longer headers

dsp rework: finished engine HEADER_OFFSET stuff, add post_engine_buffering

dsp_engine: work with transport header

dsp: 8 to 16 bit conversion for tx side. believed to be functional

dsp rework: added double buffer interface to vita tx

dsp rework: top level fixes B100/E100

dsp rework: implemented dsp changes for other top levels

added user registers into each toplevel (not used yet)

dsp rework: u2_core test implementation

b100: bumped fpga compat number for slave fifo mode

B100: moar buffering on TX for better performance in bidirectional applications

n2xx: updated bootloader to latest build in uhd master

need more umph out of correction values

convenience makefiles for top level projects

dsp: remove dsp_buffer and replace with simpler add_routing_header,
other funcs of dsp_buffer are done by double_buffer and dsp_engine

u1e: fix unattached nets from copy-paste error

b100: remove test features from GPIF to save space

forgot to add gpio atr to makefile source list

u1e/u1p: removed led setting reg

u2/u2p: use new setting_reg based gpios, gets it off of wb

u2/u2p: move nearly all setting regs onto dsp_clk

dsp: make rounding a single bit work again

dsp_engine: don't use SD rounding in 8 bit mode, so we can have a flat noise floor.

dsp_engine fix rst -> reset, default to read address

dspengine: insert into the rx chain

dsp: ability to set rx dc offset to a fixed value

connect and map b100 and e100 front-panel leds

E100: GPSDO serial port level conversion

u1e,u1p: turn off debug pins, misc cleanups

u1e: relax GPMC constraints, eases P&R

e100: squashed work on bus implementation on GPMC

fpga: minor tweaks to build system

all: tie unused ram inputs to 1 instead of zero, helps routing

dsp: slow down the time constant of the DC offset correction by a factor of 16. it may need to be even slower.

e100: continuation of the atr fix to get e100 to build