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root / usrp2 / fifo @ cc1a3502

Name Size
.gitignore 6 Bytes
Makefile.srcs 500 Bytes
buffer_int.v 3.7 kB
buffer_int_tb.v 8.8 kB
buffer_pool.v 10.3 kB
buffer_pool_tb.v 2.1 kB
fifo19_to_fifo36.v 1.6 kB
fifo19_to_ll8.v 1.2 kB
fifo36_demux.v 1.4 kB
fifo36_mux.v 1.5 kB
fifo36_to_fifo18.v 1 kB
fifo36_to_fifo19.v 1.1 kB
fifo36_to_ll8.v 1.4 kB
fifo_2clock.v 4 kB
fifo_2clock_cascade.v 1.6 kB
fifo_cascade.v 1.8 kB
fifo_long.v 3.1 kB
fifo_new_tb.vcd 52.4 kB
fifo_short.v 1.9 kB
fifo_spec.txt 938 Bytes
fifo_tb.v 3.8 kB
ll8_shortfifo.v 567 Bytes
ll8_to_fifo19.v 1.9 kB
ll8_to_fifo36.v 2.1 kB

Latest revisions

# Date Author Comment
6d2d62ca 03/25/2012 08:23 pm Josh Blum

fpga: fifo_2clock handles widths and sizes in-between corgens
ca02bf03 11/05/2011 06:04 am Matt Ettus

dsp: remove dsp_buffer and replace with simpler add_routing_header,
other funcs of dsp_buffer are done by double_buffer and dsp_engine
311fcf1a 08/26/2011 08:24 pm Matt Ettus

all: tie unused ram inputs to 1 instead of zero, helps routing
0f50e9de 07/19/2011 08:49 pm Josh Blum

usrp2: split inspection logic into each relevant cycle
bfaa5d14 06/08/2011 02:42 am Josh Blum

added copyrights
79596926 05/27/2011 12:35 am Matt Ettus

u2p-rebase: go back to versions on next
f5ef9116 05/27/2011 12:31 am Matt Ettus

u1p: pass tx status/error packets back through GPIF over the response channel (short packets)
a4dc4a53 05/27/2011 12:31 am Matt Ettus

u1p: use 18 bit fifos and use full size of a block ram in the tx path
0ce67c4b 05/27/2011 12:31 am Matt Ettus

pad out packets to a minimum length
a9f3336e 05/27/2011 12:31 am Matt Ettus

add padding into gpif response path

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