Revision c811e886

b/control_lib/newfifo/fifo_2clock_cascade.v
17 17 
      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
18 18 
      .space(s1_space), .occupied(s1_occupied) );
19 19
20 
   fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
20 
   fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
21 21 
     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
22 22 
      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
23 23 
      .arst(arst) );
b/simple_gemac/eth_tasks_f36.v
5 5 
   begin
6 6 
      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
7 7 
      pause_time <= fc_len;
8 
      @(posedge clk);
8 
      @(posedge eth_clk);
9 9 
      pause_req <= 1;
10 
      @(posedge clk);
10 
      @(posedge eth_clk);
11 11 
      pause_req <= 0;
12 12 
      $display("Sent Flow Control");
13 13 
   end
......
20 20 
   begin
21 21 
      $display("Sending Packet Len=%d, %d", data_len, $time);
22 22 
      count   <= 2;
23 
      tx_f36_dat <= {2'b0, 1'b0, 1'b1, data_start};
23 
      tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
24 24 
      tx_f36_src_rdy  <= 1;
25 25 
      #1;
26 26 
      while(count < data_len)
27 27 
	begin
28 28 
	   while(~tx_f36_dst_rdy)
29 
	     @(posedge clk);
30 
	   @(posedge clk);
31 
	   tx_f36_dat[31:0] = tx_f36_dat[31:0] + 32'h0101_0101;
29 
	     @(posedge sys_clk);
30 
	   @(posedge sys_clk);
31 
	   tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
32 32 
	   count 	   = count + 4;
33 
	   tx_f36_dat[32] <= 0;
33 
	   tx_f36_data[32] <= 0;
34 34 
	end
35 
      tx_f36_dat[3] 	  <= 1;
35 
      tx_f36_data[33] 	  <= 1;
36 36 
      while(~tx_f36_dst_rdy)
37 
	@(posedge clk);
38 
      @(posedge clk);
37 
	@(posedge sys_clk);
38 
      @(posedge sys_clk);
39 39 
      tx_f36_src_rdy <= 0;
40 40 
   end
41 41 
endtask // SendPacket_to_fifo36
42 42 

  		




  43
  
  
    

  		




  
  43
  
    
/*


  		




  44
  44
  
    
task Waiter;


  		




  45
  45
  
    
   input [31:0] wait_length;


  		




  46
  46
  
    
   begin


  		




  ......




  50
  50
  
    
      tx_ll_src_rdy2 <= 1;


  		




  51
  51
  
    
   end


  		




  52
  52
  
    
endtask // Waiter


  		




  
  53
  
    
*/


  		




  53
  54
  
    

  		




  
  55
  
    
/*


  		




  54
  56
  
    
task SendPacketFromFile_f36;


  		




  55
  57
  
    
   input [31:0] data_len;


  		




  56
  58
  
    
   input [31:0] wait_length;


  		




  ......




  63
  65
  
    

  		




  64
  66
  
    
      while(~tx_f36_dst_rdy)


  		




  65
  67
  
    
	@(posedge clk);


  		




  66
  
  
    
      tx_f36_data2 <= pkt_rom[0];


  		




  
  68
  
    
      tx_f36_data <= pkt_rom[0];


  		




  67
  69
  
    
      tx_f36_src_rdy <= 1;


  		




  68
  
  
    
      tx_ll_eof2     <= 0;


  		




  
  70
  
    
      tx_f36_eof     <= 0;


  		




  69
  71
  
    
      @(posedge clk);


  		




  70
  72
  
    
      


  		




  71
  73
  
    
      for(i=1;i<data_len-1;i=i+1)


  		




  ......




  75
  77
  
    
	   tx_ll_data2 <= pkt_rom[i];


  		




  76
  78
  
    
	   tx_ll_sof2  <= 0;


  		




  77
  79
  
    
	   @(posedge clk);


  		




  78
  
  
    
	   if(i==wait_time)


  		




  79
  
  
    
	     Waiter(wait_length);


  		




  
  80
  
    
//	   if(i==wait_time)


  		




  
  81
  
    
//	     Waiter(wait_length);


  		




  80
  82
  
    
	end


  		




  81
  83
  
    
      


  		




  82
  84
  
    
      while(~tx_ll_dst_rdy2)


  		




  ......




  87
  89
  
    
      tx_ll_src_rdy2 <= 0;


  		




  88
  90
  
    
   end


  		




  89
  91
  
    
endtask


  		




  
  92
  
    
*/


  		












  

    
      b/simple_gemac/simple_gemac_wrapper.build
    
  





  
  1
  
    
iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v


  		












  

    
      b/simple_gemac/simple_gemac_wrapper_tb.v
    
  





  1
  1
  
    

  		




  2
  2
  
    

  		




  3
  3
  
    
module simple_gemac_wrapper_tb;


  		




  4
  
  
    
`include "eth_tasks.v"


  		




  
  4
  
    
`include "eth_tasks_f36.v"


  		




  5
  5
  
    
     


  		




  6
  
  
    
   reg clk     = 0;


  		




  7
  6
  
    
   reg reset   = 1;


  		




  8
  
  
    

  		




  9
  7
  
    
   initial #1000 reset = 0;


  		




  10
  
  
    
   always #50 clk = ~clk;


  		




  
  8
  
    
   wire wb_rst 	= reset;


  		




  
  9
  
    

  		




  
  10
  
    
   reg eth_clk     = 0;


  		




  
  11
  
    
   always #50 eth_clk = ~eth_clk;


  		




  11
  12
  
    

  		




  12
  13
  
    
   reg wb_clk 	= 0;


  		




  13
  
  
    
   wire wb_rst 	= reset;


  		




  14
  14
  
    
   always #173 wb_clk = ~wb_clk;


  		




  15
  
  
    
       


  		




  
  15
  
    

  		




  
  16
  
    
   reg sys_clk 	= 0;


  		




  
  17
  
    
   always #77 sys_clk = ~ sys_clk;


  		




  
  18
  
    
   


  		




  16
  19
  
    
   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;


  		




  17
  20
  
    
   wire [7:0] GMII_RXD, GMII_TXD;


  		




  18
  21
  
    

  		




  ......




  35
  38
  
    
   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;


  		




  36
  39
  
    

  		




  37
  40
  
    

  		




  38
  
  
    
   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;


  		




  39
  
  
    
   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;


  		




  40
  
  
    
   reg rx_ll_dst_rdy2 = 1;


  		




  41
  
  
    
   wire [7:0] rx_ll_data, rx_ll_data2;


  		




  42
  
  
    
   wire rx_ll_error, rx_ll_error2;


  		




  43
  
  
    

  		




  44
  41
  
    
   wire [31:0] wb_dat_o;


  		




  45
  42
  
    
   reg [31:0]  wb_dat_i;


  		




  46
  43
  
    
   reg [7:0]   wb_adr;


  		




  47
  44
  
    
   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;


  		




  48
  45
  
    
   wire        wb_ack;


  		




  
  46
  
    

  		




  
  47
  
    
   reg [35:0]  tx_f36_data=0;


  		




  
  48
  
    
   reg 	       tx_f36_src_rdy=0;


  		




  
  49
  
    
   wire        tx_f36_dst_rdy;


  		




  49
  50
  
    
   


  		




  50
  51
  
    
   simple_gemac_wrapper simple_gemac_wrapper


  		




  51
  
  
    
     (.clk125(clk),  .reset(reset),


  		




  
  52
  
    
     (.clk125(eth_clk),  .reset(reset),


  		




  52
  53
  
    
      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  


  		




  53
  54
  
    
      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),


  		




  54
  55
  
    
      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  


  		




  55
  56
  
    
      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),


  		




  56
  57
  
    
      .pause_req(pause_req), .pause_time(pause_time),


  		




  57
  
  
    
      .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),


  		




  58
  
  
    
      .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy),


  		




  59
  
  
    
      .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),


  		




  60
  
  
    
      .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy),


  		




  61
  
  
    
      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),


  		




  62
  
  
    
      .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),


  		




  63
  
  
    
      .mdio(mdio), .mdc(mdc) );


  		




  64
  
  
    

  		




  65
  
  
    
   ll8_shortfifo rx_sfifo


  		




  66
  
  
    
     (.clk(clk), .reset(reset), .clear(0),


  		




  67
  
  
    
      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),


  		




  68
  
  
    
      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),


  		




  69
  
  
    
      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),


  		




  70
  
  
    
      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));


  		




  71
  
  
    

  		




  72
  
  
    
   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;


  		




  73
  
  
    
   reg tx_ll_sof2=0, tx_ll_eof2=0;


  		




  74
  
  
    
   reg tx_ll_src_rdy2 = 0;


  		




  75
  
  
    
   wire tx_ll_dst_rdy2;


  		




  76
  
  
    
   wire [7:0] tx_ll_data;


  		




  77
  
  
    
   reg [7:0] tx_ll_data2 = 0;


  		




  78
  
  
    
   wire tx_ll_error;


  		




  79
  
  
    
   wire tx_ll_error2 = 0;


  		




  80
  
  
    

  		




  81
  
  
    
   ll8_shortfifo tx_sfifo


  		




  82
  
  
    
     (.clk(clk), .reset(reset), .clear(clear),


  		




  83
  
  
    
      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),


  		




  84
  
  
    
      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),


  		




  85
  
  
    
      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),


  		




  86
  
  
    
      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));


  		




  
  58
  
    

  		




  
  59
  
    
      .sys_clk(sys_clk), .rx_f36_data(), .rx_f36_src_rdy(), .rx_f36_dst_rdy(),


  		




  
  60
  
    
      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),


  		




  
  61
  
    

  		




  
  62
  
    
      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),


  		




  
  63
  
    
      .wb_adr(), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),


  		




  
  64
  
    

  		




  
  65
  
    
      .mdio(), .mdc(),


  		




  
  66
  
    
      .debug() );


  		




  87
  67
  
    
   


  		




  88
  68
  
    
   initial $dumpfile("simple_gemac_wrapper_tb.vcd");


  		




  89
  69
  
    
   initial $dumpvars(0,simple_gemac_wrapper_tb);


  		




  ......




  100
  80
  
    
     begin


  		




  101
  81
  
    
	@(negedge reset);


  		




  102
  82
  
    
	repeat (10)


  		




  103
  
  
    
	  @(posedge clk);


  		




  
  83
  
    
	  @(posedge wb_clk);


  		




  104
  84
  
    
	WishboneWR(0,6'b111001);


  		




  105
  85
  
    
	WishboneWR(4,16'hF1F2);


  		




  106
  86
  
    
	WishboneWR(8,32'hF3F4_F5F6);


  		




  107
  87
  
    
	WishboneWR(12,16'h0000);


  		




  108
  88
  
    
	WishboneWR(16,32'h0000_0000);


  		




  109
  89
  
    
	


  		




  110
  
  
    
	@(posedge clk);


  		




  
  90
  
    
	@(posedge eth_clk);


  		




  111
  91
  
    
	SendFlowCtrl(16'h0007);  // Send flow control


  		




  112
  
  
    
	@(posedge clk);


  		




  
  92
  
    
	@(posedge eth_clk);


  		




  113
  93
  
    
	#30000;


  		




  114
  
  
    
	@(posedge clk);


  		




  115
  
  
    
	SendFlowCtrl(16'h0009);  // Increas flow control before it expires


  		




  
  94
  
    
	@(posedge eth_clk);


  		




  
  95
  
    
	SendFlowCtrl(16'h0009);  // Increase flow control before it expires


  		




  116
  96
  
    
	#10000;


  		




  117
  
  
    
	@(posedge clk);


  		




  
  97
  
    
	@(posedge eth_clk);


  		




  118
  98
  
    
	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires


  		




  119
  
  
    
	@(posedge clk); 


  		




  
  99
  
    
	@(posedge eth_clk); 


  		




  120
  100
  
    

  		




  121
  
  
    
	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters


  		




  122
  
  
    
	repeat (10)


  		




  123
  
  
    
	  @(posedge clk);


  		




  
  101
  
    
	repeat (1000)


  		




  
  102
  
    
	  @(posedge sys_clk);


  		




  
  103
  
    
	SendPacket_to_fifo36(32'hAABBCCDD,10);    // This packet gets dropped by the filters


  		




  
  104
  
    
	repeat (1000)


  		




  
  105
  
    
	  @(posedge sys_clk);


  		




  124
  106
  
    

  		




  125
  
  
    
 	SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets


  		




  
  107
  
    
	SendPacket_to_fifo36(32'hAABBCCDD,100);    // This packet gets dropped by the filters


  		




  
  108
  
    
	repeat (10)


  		




  
  109
  
    
	  @(posedge sys_clk);


  		




  
  110
  
    
/*


  		




  
  111
  
    
 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets


  		




  126
  112
  
    
	repeat (10)


  		




  127
  113
  
    
	  @(posedge clk);


  		




  128
  114
  
    

  		




  129
  
  
    
 	SendPacketFromFile_ll8(61,0,0);


  		




  
  115
  
    
 	SendPacketFromFile_f36(61,0,0);


  		




  130
  116
  
    
	repeat (10)


  		




  131
  117
  
    
	  @(posedge clk);


  		




  132
  
  
    
	SendPacketFromFile_ll8(62,0,0);


  		




  
  118
  
    
	SendPacketFromFile_f36(62,0,0);


  		




  133
  119
  
    
	repeat (10)


  		




  134
  120
  
    
	  @(posedge clk);


  		




  135
  
  
    
	SendPacketFromFile_ll8(63,0,0);


  		




  
  121
  
    
	SendPacketFromFile_f36(63,0,0);


  		




  136
  122
  
    
	repeat (1)


  		




  137
  123
  
    
	  @(posedge clk);


  		




  138
  
  
    
	SendPacketFromFile_ll8(64,0,0);


  		




  
  124
  
    
	SendPacketFromFile_f36(64,0,0);


  		




  139
  125
  
    
	repeat (10)


  		




  140
  126
  
    
	  @(posedge clk);


  		




  141
  
  
    
	SendPacketFromFile_ll8(59,0,0);


  		




  
  127
  
    
	SendPacketFromFile_f36(59,0,0);


  		




  142
  128
  
    
	repeat (1)


  		




  143
  129
  
    
	  @(posedge clk);


  		




  144
  
  
    
	SendPacketFromFile_ll8(58,0,0);


  		




  
  130
  
    
	SendPacketFromFile_f36(58,0,0);


  		




  145
  131
  
    
	repeat (1)


  		




  146
  132
  
    
	  @(posedge clk);


  		




  147
  
  
    
	SendPacketFromFile_ll8(100,0,0);


  		




  
  133
  
    
	SendPacketFromFile_f36(100,0,0);


  		




  148
  134
  
    
	repeat (1)


  		




  149
  135
  
    
	  @(posedge clk);


  		




  150
  
  
    
	SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns


  		




  
  136
  
    
	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns


  		




  151
  137
  
    
	repeat (1)


  		




  152
  138
  
    
	  @(posedge clk);


  		




  153
  
  
    
	SendPacketFromFile_ll8(100,0,30);


  		




  154
  
  
    
	#10000 $finish;


  		




  
  139
  
    
	SendPacketFromFile_f36(100,0,30);


  		




  
  140
  
    
 */


  		




  
  141
  
    
	#100000 $finish;


  		




  155
  142
  
    
     end


  		




  156
  143
  
    

  		




  157
  144
  
    
   // Force a CRC error


  		




  158
  145
  
    
    initial


  		




  159
  146
  
    
     begin


  		




  160
  147
  
    
	#90000;


  		




  161
  
  
    
	@(posedge clk);


  		




  
  148
  
    
	@(posedge eth_clk);


  		




  162
  149
  
    
	FORCE_DAT_ERR <= 8'h10;


  		




  163
  
  
    
	@(posedge clk);


  		




  
  150
  
    
	@(posedge eth_clk);


  		




  164
  151
  
    
	FORCE_DAT_ERR <= 8'h00;


  		




  165
  152
  
    
     end


  		




  166
  153
  
    

  		




  ......




  168
  155
  
    
   initial


  		




  169
  156
  
    
     begin


  		




  170
  157
  
    
	#116000;


  		




  171
  
  
    
	@(posedge clk);


  		




  
  158
  
    
	@(posedge eth_clk);


  		




  172
  159
  
    
	FORCE_ERR <= 1;


  		




  173
  
  
    
	@(posedge clk);


  		




  
  160
  
    
	@(posedge eth_clk);


  		




  174
  161
  
    
	FORCE_ERR <= 0;


  		




  175
  162
  
    
     end


  		




  176
  
  
    

  		




  
  163
  
    
/*


  		




  177
  164
  
    
   // Cause receive fifo to fill, causing an RX overrun


  		




  178
  165
  
    
   initial


  		




  179
  166
  
    
     begin


  		




  ......




  184
  171
  
    
	  @(posedge clk);


  		




  185
  172
  
    
	rx_ll_dst_rdy2 <= 1;


  		




  186
  173
  
    
     end


  		




  187
  
  
    
   


  		




  
  174
  
    
  */


  		




  188
  175
  
    
   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun


  		




  189
  176
  
    
   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone


  		




  190
  177
  
    

  		




  ......




  205
  192
  
    
	 wb_we 	<= 0;


  		




  206
  193
  
    
      end


  		




  207
  194
  
    
   endtask // WishboneWR


  		




  208
  
  
    
   


  		




  
  195
  
    
   /*


  		




  209
  196
  
    
   always @(posedge clk)


  		




  210
  197
  
    
     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)


  		




  211
  198
  
    
       begin


  		




  ......




  215
  202
  
    
	  if(rx_ll_eof2 & ~rx_ll_sof2)


  		




  216
  203
  
    
	    $display("RX-PKT-END %d",$time);


  		




  217
  204
  
    
       end


  		




  218
  
  
    
   


  		




  
  205
  
    
   */


  		




  219
  206
  
    
endmodule // simple_gemac_wrapper_tb


  		












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