fpga

vita: moved clear register to overlap with nchan register

This fixes the bug where setting the format clears the vita RX.
This is only an issue when the noclear option is set by UHD,
because the format register is always so, so it always clears.
Note: noclear is there to support the backwards compat API (pre streamer)....

b100: fix slave fifo data xfer exit condition

When exiting the read/write data state,
when the transfer count maxes out/peaks,
the fifo read/write signals were getting this
condition the cycle after with the state change.

B100: port cleanups from b100-txbug to this branch

b100: cleanup redundant logic for slwr and slrd

b100: slave fifo fix for dst/src ready signals

Some of the changes my be overkill,
but the idea is to be more careful about
allowing FIFO IO to occur on transitions.

The cal app was able to complete successfully.