Revision 7c057ae2 usrp2/top/u2_rev3/u2_core_udp.v

b/usrp2/top/u2_rev3/u2_core_udp.v
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       cycle_count <= cycle_count + 1;
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   //compatibility number -> increment when the fpga has been sufficiently altered


  		





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   localparam compat_num = 32'd1;


  		





  
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   localparam compat_num = 32'd2;


  		





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   wb_readback_mux buff_pool_status


  		





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     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),


  		












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