Revision 7bf8a6df
| ID | 7bf8a6df381a667134b55701993c6770d32bc76b |
Moved usrp2 fpga files into usrp2 subdir.
Files
- added
- modified
- copied
- renamed
- deleted
- boot_cpld
- .gitignore
- _impact.cmd
- boot_cpld.ipf
- boot_cpld.ise
- boot_cpld.lfp
- boot_cpld.ucf
- boot_cpld.v
- control_lib
- .gitignore
- CRC16_D16.v
- SYSCTRL.sav
- WB_SIM.sav
- atr_controller.v
- bin2gray.v
- bootrom.mem
- clock_bootstrap_rom.v
- clock_control.v
- clock_control_tb.sav
- clock_control_tb.v
- cmdfile
- dcache.v
- decoder_3_8.v
- dpram32.v
- fifo_tb.v
- gray2bin.v
- gray_send.v
- icache.v
- longfifo.v
- medfifo.v
- mux4.v
- mux8.v
- mux_32_4.v
- newfifo
- .gitignore
- buffer_int.v
- buffer_int_tb.v
- buffer_pool.v
- buffer_pool_tb.v
- fifo19_to_fifo36.v
- fifo19_to_ll8.v
- fifo36_to_fifo18.v
- fifo36_to_fifo19.v
- fifo36_to_ll8.v
- fifo_2clock.v
- fifo_2clock_cascade.v
- fifo_cascade.v
- fifo_long.v
- fifo_new_tb.vcd
- fifo_short.v
- fifo_spec.txt
- fifo_tb.v
- ll8_shortfifo.v
- ll8_to_fifo19.v
- ll8_to_fifo36.v
- nsgpio.v
- oneshot_2clk.v
- pic.v
- priority_enc.v
- ram_2port.v
- ram_harv_cache.v
- ram_loader.v
- ram_wb_harvard.v
- reset_sync.v
- sd_spi.v
- sd_spi_tb.v
- sd_spi_wb.v
- setting_reg.v
- settings_bus.v
- shortfifo.v
- simple_uart.v
- simple_uart_rx.v
- simple_uart_tx.v
- spi.v
- srl.v
- ss_rcvr.v
- system_control.v
- system_control_tb.v
- traffic_cop.v
- wb_1master.v
- wb_bridge_16_32.v
- wb_bus_writer.v
- wb_output_pins32.v
- wb_ram_block.v
- wb_ram_dist.v
- wb_readback_mux.v
- wb_regfile_2clock.v
- wb_semaphore.v
- wb_sim.v
- coregen
- .gitignore
- coregen.cgp
- fifo_generator_release_notes.txt
- fifo_generator_ug175.pdf
- fifo_xlnx_16x19_2clk.ngc
- fifo_xlnx_16x19_2clk.v
- fifo_xlnx_16x19_2clk.veo
- fifo_xlnx_16x19_2clk.xco
- fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_16x19_2clk_flist.txt
- fifo_xlnx_16x19_2clk_readme.txt
- fifo_xlnx_16x19_2clk_xmdf.tcl
- fifo_xlnx_2Kx36_2clk.asy
- fifo_xlnx_2Kx36_2clk.ngc
- fifo_xlnx_2Kx36_2clk.sym
- fifo_xlnx_2Kx36_2clk.v
- fifo_xlnx_2Kx36_2clk.veo
- fifo_xlnx_2Kx36_2clk.vhd
- fifo_xlnx_2Kx36_2clk.vho
- fifo_xlnx_2Kx36_2clk.xco
- fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_2Kx36_2clk_flist.txt
- fifo_xlnx_2Kx36_2clk_readme.txt
- fifo_xlnx_2Kx36_2clk_xmdf.tcl
- fifo_xlnx_512x36_2clk.asy
- fifo_xlnx_512x36_2clk.ngc
- fifo_xlnx_512x36_2clk.sym
- fifo_xlnx_512x36_2clk.v
- fifo_xlnx_512x36_2clk.veo
- fifo_xlnx_512x36_2clk.vhd
- fifo_xlnx_512x36_2clk.vho
- fifo_xlnx_512x36_2clk.xco
- fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_512x36_2clk_flist.txt
- fifo_xlnx_512x36_2clk_readme.txt
- fifo_xlnx_512x36_2clk_xmdf.tcl
- fifo_xlnx_64x36_2clk.ngc
- fifo_xlnx_64x36_2clk.v
- fifo_xlnx_64x36_2clk.veo
- fifo_xlnx_64x36_2clk.xco
- fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_64x36_2clk_flist.txt
- fifo_xlnx_64x36_2clk_readme.txt
- fifo_xlnx_64x36_2clk_xmdf.tcl
- extram
- .gitignore
- extram_interface.v
- extram_wb.v
- wb_zbt16_b.v
- models
- BUFG.v
- CY7C1356C
- cy1356.inp
- cy1356.v
- readme.txt
- testbench.v
- FIFO_GENERATOR_V4_3.v
- M24LC024B.v
- M24LC02B.v
- MULT18X18S.v
- RAMB16_S36_S36.v
- SRL16E.v
- SRLC16E.v
- adc_model.v
- cpld_model.v
- math_real.v
- miim_model.v
- phy_sim.v
- serdes_model.v
- uart_rx.v
- xlnx_glbl.v
- opencores
- 8b10b
- .gitignore
- 8b10b_a.mem
- README
- decode_8b10b.v
- encode_8b10b.v
- validate_8b10b.v
- README
- aemb
- i2c
- simple_gpio
- simple_pic
- spi
- spi_boot
- COMPILE_LIST
- COPYING
- CVS
- Entries
- Repository
- Root
- Template
- KNOWN_BUGS
- README
- bench
- doc
- rtl
- CVS
- Entries
- Repository
- Root
- Template
- vhdl
- CVS
- Entries
- Repository
- Root
- Template
- chip-e.vhd
- chip-full-a.vhd
- chip-full-c.vhd
- chip-minimal-a.vhd
- chip-minimal-c.vhd
- chip-mmc-a.vhd
- chip-mmc-c.vhd
- chip-sd-a.vhd
- chip-sd-c.vhd
- sample
- CVS
- Entries
- Repository
- Root
- Template
- ram_loader-c.vhd
- ram_loader.vhd
- CVS
- spi_boot-c.vhd
- spi_boot.vhd
- spi_boot_pack-p.vhd
- spi_counter-c.vhd
- spi_counter.vhd
- CVS
- CVS
- sim
- sw
- wb_zbt
- CVS
- Entries
- Repository
- Root
- Template
- wb_zbt.v
- CVS
- 8b10b
- sdr_lib
- .gitignore
- HB.sav
- SMALL_HB.sav
- acc.v
- add2.v
- add2_and_round.v
- add2_and_round_reg.v
- add2_reg.v
- cic_dec_shifter.v
- cic_decim.v
- cic_int_shifter.v
- cic_interp.v
- cic_strober.v
- clip.v
- clip_and_round.v
- clip_and_round_reg.v
- clip_reg.v
- cordic.v
- cordic_stage.v
- cordic_z24.v
- ddc.v
- dsp_core_rx.v
- dsp_core_tx.v
- duc.v
- dummy_rx.v
- gen_cordic_consts.py
- halfband_ideal.v
- halfband_tb.v
- hb
- acc.v
- coeff_ram.v
- coeff_rom.v
- halfband_decim.v
- halfband_interp.v
- hbd_tb
- HBD
- really_golden
- regression
- run_hbd
- test_hbd.v
- mac.v
- mult.v
- ram16_2port.v
- ram16_2sum.v
- ram32_2sum.v
- hb_dec.v
- hb_dec_tb.v
- hb_interp.v
- hb_interp_tb.v
- hb_tb.v
- input.dat
- integrate.v
- med_hb_int.v
- output.dat
- round.v
- round_reg.v
- rssi.v
- rx_control.v
- rx_dcoffset.v
- rx_dcoffset_tb.v
- sign_extend.v
- small_hb_dec.v
- small_hb_dec_tb.v
- small_hb_int.v
- small_hb_int_tb.v
- tx_control.v
- serdes
- serdes.v
- serdes_fc_rx.v
- serdes_fc_tx.v
- serdes_rx.v
- serdes_tb.v
- serdes_tx.v
- simple_gemac
- .gitignore
- address_filter.v
- crc.v
- delay_line.v
- eth_tasks.v
- eth_tasks_f36.v
- flow_ctrl_rx.v
- flow_ctrl_tx.v
- ll8_shortfifo.v
- ll8_to_txmac.v
- miim
- eth_clockgen.v
- eth_miim.v
- eth_outputcontrol.v
- eth_shiftreg.v
- rxmac_to_ll8.v
- simple_gemac.v
- simple_gemac_rx.v
- simple_gemac_tb.v
- simple_gemac_tx.v
- simple_gemac_wb.v
- simple_gemac_wrapper.build
- simple_gemac_wrapper.v
- simple_gemac_wrapper_f36_tb.v
- simple_gemac_wrapper_tb.v
- test_packet.mem
- testbench
- .gitignore
- BOOTSTRAP.sav
- Makefile
- PAUSE.sav
- README
- SERDES.sav
- U2_SIM.sav
- cmdfile
- timing
- .gitignore
- time_64bit.v
- time_receiver.v
- time_sender.v
- time_sync.v
- time_transfer_tb.v
- timer.v
- top
- .gitignore
- eth_test
- .gitignore
- eth_sim_top.v
- eth_tb.v
- single_u2_sim
- single_u2_sim.v
- tcl
- ise_helper.tcl
- u2_core
- .gitignore
- u2_core.v
- u2_rev1
- .gitignore
- Makefile
- u2_fpga.ise
- u2_fpga.ucf
- u2_fpga_top.prj
- u2_fpga_top.v
- u2_rev2
- .gitignore
- Makefile
- u2_rev2.ucf
- u2_rev2.v
- u2_rev3
- .gitignore
- Makefile
- u2_rev3.ucf
- u2_rev3.v
- u2_rev3_2rx_iad
- Makefile
- README
- cmdfile
- dsp_core_rx.v
- dsp_core_tb.sav
- dsp_core_tb.v
- impulse.v
- u2_core.v
- wave.sh
- u2_rev3_iad
- .gitignore
- Makefile
- cmdfile
- dsp_core_rx.v
- dsp_core_tb.sav
- dsp_core_tb.v
- impulse.v
- wave.sh
- u2plus
- u2plus.ucf
- u2plus.v
- usrp2
- boot_cpld
- control_lib
- .gitignore
- CRC16_D16.v
- atr_controller.v
- bin2gray.v
- bootrom.mem
- clock_bootstrap_rom.v
- clock_control.v
- clock_control_tb.v
- cmdfile
- dcache.v
- decoder_3_8.v
- dpram32.v
- fifo_tb.v
- gray2bin.v
- gray_send.v
- icache.v
- longfifo.v
- medfifo.v
- mux4.v
- mux8.v
- mux_32_4.v
- newfifo
- .gitignore
- buffer_int.v
- buffer_int_tb.v
- buffer_pool.v
- buffer_pool_tb.v
- fifo19_to_fifo36.v
- fifo19_to_ll8.v
- fifo36_to_fifo18.v
- fifo36_to_fifo19.v
- fifo36_to_ll8.v
- fifo_2clock.v
- fifo_2clock_cascade.v
- fifo_cascade.v
- fifo_long.v
- fifo_new_tb.vcd
- fifo_short.v
- fifo_spec.txt
- fifo_tb.v
- ll8_shortfifo.v
- ll8_to_fifo19.v
- ll8_to_fifo36.v
- nsgpio.v
- oneshot_2clk.v
- pic.v
- priority_enc.v
- ram_2port.v
- ram_harv_cache.v
- ram_loader.v
- ram_wb_harvard.v
- reset_sync.v
- sd_spi.v
- sd_spi_tb.v
- sd_spi_wb.v
- setting_reg.v
- settings_bus.v
- shortfifo.v
- simple_uart.v
- simple_uart_rx.v
- simple_uart_tx.v
- spi.v
- srl.v
- ss_rcvr.v
- system_control.v
- system_control_tb.v
- traffic_cop.v
- wb_1master.v
- wb_bridge_16_32.v
- wb_bus_writer.v
- wb_output_pins32.v
- wb_ram_block.v
- wb_ram_dist.v
- wb_readback_mux.v
- wb_regfile_2clock.v
- wb_semaphore.v
- wb_sim.v
- coregen
- .gitignore
- coregen.cgp
- fifo_generator_release_notes.txt
- fifo_generator_ug175.pdf
- fifo_xlnx_16x19_2clk.ngc
- fifo_xlnx_16x19_2clk.v
- fifo_xlnx_16x19_2clk.veo
- fifo_xlnx_16x19_2clk.xco
- fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_16x19_2clk_flist.txt
- fifo_xlnx_16x19_2clk_readme.txt
- fifo_xlnx_16x19_2clk_xmdf.tcl
- fifo_xlnx_2Kx36_2clk.asy
- fifo_xlnx_2Kx36_2clk.ngc
- fifo_xlnx_2Kx36_2clk.sym
- fifo_xlnx_2Kx36_2clk.v
- fifo_xlnx_2Kx36_2clk.veo
- fifo_xlnx_2Kx36_2clk.vhd
- fifo_xlnx_2Kx36_2clk.vho
- fifo_xlnx_2Kx36_2clk.xco
- fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_2Kx36_2clk_flist.txt
- fifo_xlnx_2Kx36_2clk_readme.txt
- fifo_xlnx_2Kx36_2clk_xmdf.tcl
- fifo_xlnx_512x36_2clk.asy
- fifo_xlnx_512x36_2clk.ngc
- fifo_xlnx_512x36_2clk.sym
- fifo_xlnx_512x36_2clk.v
- fifo_xlnx_512x36_2clk.veo
- fifo_xlnx_512x36_2clk.vhd
- fifo_xlnx_512x36_2clk.vho
- fifo_xlnx_512x36_2clk.xco
- fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_512x36_2clk_flist.txt
- fifo_xlnx_512x36_2clk_readme.txt
- fifo_xlnx_512x36_2clk_xmdf.tcl
- fifo_xlnx_64x36_2clk.ngc
- fifo_xlnx_64x36_2clk.v
- fifo_xlnx_64x36_2clk.veo
- fifo_xlnx_64x36_2clk.xco
- fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
- fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
- fifo_xlnx_64x36_2clk_flist.txt
- fifo_xlnx_64x36_2clk_readme.txt
- fifo_xlnx_64x36_2clk_xmdf.tcl
- extram
- models
- opencores