Revision 4f79676f usrp2/vrt/vita_rx_framer.v

b/usrp2/vrt/vita_rx_framer.v
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       VITA_PAYLOAD :
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	 // Write if sample ready and no error flags
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     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
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       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
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       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
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	 req_write_pkt_fifo <= 1;
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       default :
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	 req_write_pkt_fifo <= 0;
......
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				   ( ((vita_state==VITA_PAYLOAD) &
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				      (sample_phase == (numchan-4'd1)) &
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				      ~|flags_fifo_o[3:1]) |
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				     (vita_state==VITA_ERR_TRAILER));
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				     (vita_state==VITA_ERR_PAYLOAD));
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   assign debug_rx  = vita_state;
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