Revision 42a98490

b/usrp2/vrt/vita_rx.build
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iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
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iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
b/usrp2/vrt/vita_rx_tb.v
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module vita_rx_tb;
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   localparam DECIM  = 8'd4;
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   localparam MAXCHAN=4;
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   localparam NUMCHAN=4;
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   localparam MAXCHAN=1;
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   localparam NUMCHAN=1;
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   reg clk 	     = 0;
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   reg reset 	     = 1;
......
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	@(posedge clk);
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	write_setting(4,32'hDEADBEEF);  // VITA header
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	write_setting(5,32'hF00D1234);  // VITA streamid
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	write_setting(6,32'h98765432);  // VITA trailer
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	write_setting(6,32'hF0000000);  // VITA trailer
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	write_setting(7,8);  // Samples per VITA packet
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	write_setting(8,NUMCHAN);  // Samples per VITA packet
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	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
......
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	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
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	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
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	#100000;
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	$display("\nChained, break chain\n");
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	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
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	#100000;
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	$display("\nSingle packet\n");
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	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
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	#100000;
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	$display("\nEnd chain with zero samples, shouldn't error\n");
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	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
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	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error

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