Merge branch 'maint'
vita: moved clear register to overlap with nchan register
This fixes the bug where setting the format clears the vita RX.This is only an issue when the noclear option is set by UHD,because the format register is always so, so it always clears.Note: noclear is there to support the backwards compat API (pre streamer)....
b100: fix slave fifo data xfer exit condition
When exiting the read/write data state,when the transfer count maxes out/peaks,the fifo read/write signals were getting thiscondition the cycle after with the state change.
fpga: extract usage summary from map file
B100: port cleanups from b100-txbug to this branch
fpga: fifo_2clock handles widths and sizes in-between corgens
b100: cleanup redundant logic for slwr and slrd
b100: extra data pktend cycle for fifo addr
b100: slave fifo fix for dst/src ready signals
Some of the changes my be overkill,but the idea is to be more careful aboutallowing FIFO IO to occur on transitions.
The cal app was able to complete successfully.
fpga: force -include_global for custom sources
ISE will not recognize custom sources as part of the hierarchy,and thus will not compile (unless its the first macro...).
Remove custom sources from the source list,and specially add them with the -include_global option.
fpga: fix custom defs in some top level makefiles
usrp2/nseries: added churn to meet timing
Added churn to readback mux on nseries to make n200r4 meet timing.Also added churn to usrp2 for parallelism, but assigned to zero.
vita rx: trigger clear after packet tranfer
To avoid blocking conditions down the pipe,avoid clearing vita rx during packet transfer.
Adds state machine to delay the clear until after xfer completes.
dsp rework: fix dspengine_8to16 to handle padded packets
dsp_engine: fix for upper/lower swap, and odd length packets
dsp rework: added flusher to vita tx chain on clear
dsp rework: minor simplification in vita_tx_deframer
all n-series devices meet timing
dsp rework: full-rate pipelining in vita tx deframer
The vita tx deframer can now pass payload at clock rate.This enables TX streaming at interpolations factors of 2.
The vector capabilities of TX deframer have been kept in-tact,and should be functional, however, only MAXCHAN=1 has been tested.
dsp rework: pass enables into glue, update power trig, parameterize, fix module inc
DSP enables now pass through the glue and custom modules so it can be user-controlled.
Updated power trigger to current spec, and added comments
Pass width from dsp into glue, and use width to parameterize wires...
dsp rework: implement 64 bit ticks no seconds
B100: External FPGA reset from FX2 reuses fpga_cfg_cclk.
dsp rework: pass vita clears into dsp modules, unified fifo clears
b100: timing constraints on GPIF lines
b100: connect all clears for gpif
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