Activity
From 06/26/2011 to 08/24/2011
08/24/2011
- 10:43 pm Bug #596 (Rejected): ram_2port.v flopping order
- 10:42 pm Bug #595 (Rejected): fifo_2clock_cascade reset
Add synchronous as well as async resets
08/16/2011
08/15/2011
- 10:37 pm Revision 8c8da195: N2x0: delay ADC A inversion so A and B are latched in the same
- 10:37 pm Revision 3e626170: usrp2: bump FPGA minor number to 2 for patch release
- 10:37 pm Revision cb1c39a6: connect unused BRAM inputs to 1s to save routing logic
- 10:37 pm Revision c5c5bacb: N2x0: added a Makefile to build all N2x0 projects (make -j4)
- 10:37 pm Revision 0dcd0fd4: N2x0: print constraints summary from makefile
- 10:37 pm Revision edbdb0bf: dsp: clear cic_decim when not enabled
08/10/2011
07/28/2011
- 08:17 pm Revision 43087d47: time: register time output to help fpga timing
- 07:08 pm Revision 16f33c73: vrt: delay the late signal to help with timing
- 06:28 pm Revision 003664fe: dsp: allow tx iq balance to be removed at compile time
- 05:53 pm Revision 321305a6: dsp: option to remove iq compensation at compile time
- 05:50 pm Revision 8925263f: time64: reverted mimo sync changes to time64
- 05:02 pm Revision b23ac38d: u2/u2p: speed up time_64, and remove readbacks on simple_gemac wb regs
- 04:18 pm Revision b57d39b9: simple_gemac: remove old 19-bit wide wrapper
- 04:15 pm Revision 9c796fb4: usrp2: remove old unused readback mux value
- 07:55 am Revision 0f439aa9: usrp2: bump minor version number for changes
- 07:53 am Revision 0b7fe5b3: vita_rx_ctrl: use an extra cmd bit to signal stop
- 07:53 am Revision 64cf011b: usrp2: fixed swapped tx/rx signals for nsgpio
- 02:44 am Revision 253f8912: simple_gemac: add parameter to allow disabling rx flow control at compile time
07/27/2011
- 11:38 pm Revision 0d9df6c2: u2/u2p: apply atr/gpio changes to u2p
- 10:41 pm Revision 4b78e1ae: atr: forgot to delete this line
- 10:30 pm Revision 556a943d: u2: redo the atr gpio pins, remove some old cruft
07/22/2011
07/21/2011
07/19/2011
- 08:49 pm Revision 0f50e9de: usrp2: split inspection logic into each relevant cycle
- 08:49 pm Revision 7e085dae: appease the ISE gods
- 08:49 pm Revision dbeea34b: removed wb readback of ATR, allowing it to be synthesized as luts
- 08:49 pm Revision 374bf86d: N200: detailed map report allows you to see what takes up too much space
- 08:48 pm Revision fea1298b: dsp: reduce bitwidth to help timing
- 08:48 pm Revision 049376f2: fpga: print timing report after generate bin file
- 08:48 pm Revision dd6d11c2: dsp: reset the interpolator when the rate changes, to prevent oscillation
- 08:48 pm Revision aa23e887: b100: fix for fpga syntax error on xfer_rate
- 08:47 pm Revision 05cfc2d5: Merge branch 'b100_shrink' into new_work
07/03/2011
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