Activity
From 05/21/2011 to 07/19/2011
07/19/2011
- 08:49 pm Revision 0f50e9de: usrp2: split inspection logic into each relevant cycle
- 08:49 pm Revision 7e085dae: appease the ISE gods
- 08:49 pm Revision dbeea34b: removed wb readback of ATR, allowing it to be synthesized as luts
- 08:49 pm Revision 374bf86d: N200: detailed map report allows you to see what takes up too much space
- 08:48 pm Revision fea1298b: dsp: reduce bitwidth to help timing
- 08:48 pm Revision 049376f2: fpga: print timing report after generate bin file
- 08:48 pm Revision dd6d11c2: dsp: reset the interpolator when the rate changes, to prevent oscillation
- 08:48 pm Revision aa23e887: b100: fix for fpga syntax error on xfer_rate
- 08:47 pm Revision 05cfc2d5: Merge branch 'b100_shrink' into new_work
07/03/2011
06/20/2011
- 05:25 pm Revision ad158c63: e100: proc_int should be high when interrupted
- 04:28 am Revision 4fd68de8: e100: added proc_int and buffer for async messages
- Redirected the tx_err stream into a buffer_int2,
and connected interrupt when a packet is written.
The proc_int is m...
06/17/2011
- 01:54 am Revision f5e84501: u1p: remove uart and bus testing to fit easier
- 01:14 am Revision b04c5800: u1p: remove unused ports
06/16/2011
- 11:13 pm Revision 79281872: u1e: core compile now works as a fullchip lint
- 06:31 pm Revision 10d489c3: u1p/u1e: cleanup some warnings, connect the correct clocks
06/15/2011
- 11:55 pm Revision 471c6cd2: USRP2/N2x0: incremented compat numbers for frontend work
- 11:38 pm Revision 8ec416f6: Merge branch 'usrp_e100_aux_spi' into dsp_rebase
- * usrp_e100_aux_spi:
usrp-e100: removed passthrough files, not needed w/ aux spi for clock chip
usrp-e100: make r... - 11:35 pm Revision 578df09d: u1e/u1p: new register map for new dsp
- 04:48 am Revision 9b3bd071: u1p: work in dual rx and frontend from u1e
- 04:20 am Revision 7cd986c7: u1p: new tx dsp frontend, copied from u1e
- 03:58 am Revision 948b9026: u1e-dsp: attach tx dc offset and iq balance
06/13/2011
06/10/2011
06/09/2011
- 05:00 pm Revision 4573bf14: usrp-e100: removed passthrough files, not needed w/ aux spi for clock chip
- 01:55 am Revision 903c69ff: usrp-e100: make reg_test32 persistent across resets, bump compat number
06/08/2011
- 11:05 pm Revision d0a8d325: usrp-e100: work on aux spi
- 05:55 pm Revision 8217bfca: dsp: small_hb_dec now 24 bits wide as well
- 05:55 pm Revision f335b169: dsp: do everything at 24 bits wide
- 05:55 pm Revision e0d0bbb8: u1e: update u1e to use new rx_frontend, and give it a 2nd rx dsp core
- 05:55 pm Revision d7a3b89d: dsp: added tx_frontend, instantiated in u2/u2p
- 05:55 pm Revision 5971f8e8: dsp: remove unused setting reg
- 05:52 pm Revision 554d08ae: dsp: testbenches for dsp blocks
- 05:52 pm Revision 3a4e028a: dsp: add resets for simulation purposes
- 05:52 pm Revision f21bc7ee: dsp: tx_dcoffset, not integrated yet
- 05:52 pm Revision 2edca948: dsp: do proper rounding at the end of dsp chain
- 05:52 pm Revision f2ea250d: dsp: reorganized scaling and rounding, removed multipliers (will put back in a...
- 05:52 pm Revision e0654430: dsp: use round_sd in small_hb_dec
- 05:52 pm Revision d35bbdf5: dsp: increase gain of small_hb_dec because it used to scale down by factor of ...
- 05:52 pm Revision b9b18331: dsp: no need to keep all the low order bits from the accumulator
- 05:52 pm Revision b5283ddf: dsp: register hb output
- 05:52 pm Revision 36e3085d: dsp: fix off-by-one error in timing of hb_dec
- 05:52 pm Revision 6592deb4: dsp: add guard bit to top of cordic to allow clipping on output instead of wra...
- 05:52 pm Revision b88383ad: dsp: clip in hb_dec to prevent the rare overflow with certain frequencies at m...
- 05:52 pm Revision 967ca165: u2/u2p: use all 24 bits from the rx_frontend
- 05:52 pm Revision 6c28203a: dsp: pass 24 bit wide signals between frontend and dsp core.
- Overkill, but we have the bits already, so why throw them away?
- 05:52 pm Revision 883d5af4: unused nets
- 05:52 pm Revision 2bad9b4d: u2/u2p: misc connection and compilation fixes
- 05:52 pm Revision 47967a43: dsp: pass the error through in the rounding function
- 05:52 pm Revision b9731980: dsp: first cut at sigma-delta rounding
- 05:52 pm Revision 569d9ee6: dsp: reworked round_sd, it is much simpler now
- 05:52 pm Revision 7b127e2f: dsp: use sigma delta rounding in rx_dcoffset and in dsp_core_rx
- 05:52 pm Revision 90c74cd4: u2/u2p: use new rx_frontend in u2 and u2p
- 05:52 pm Revision 56853530: dsp: add2_and_clip_reg and round_sd now are now strobed to be compatible
- with strobed (non-full rate) data
- 05:52 pm Revision 3993b882: dsp: reworked muxes on rx
- 05:52 pm Revision e78a301e: dsp: new files in dsp directory
- 05:52 pm Revision 757d06d2: dsp: more typos
- 05:52 pm Revision 2e2de3f8: dsp: fix typos
- 05:52 pm Revision ce43cdfc: redone DC offset with sigma-delta quantization
- 05:52 pm Revision f8a04a48: u2/u2p: pull IQ balance and dcoffset out of dsp_core, put in frontend module
- 02:46 am Revision 23c373f4: fix copyright notice
- 02:42 am Revision bfaa5d14: added copyrights
06/07/2011
- 11:48 pm Revision e4be5c90: lots of renaming and moving around of toplevel directories to reflect product ...
- 11:26 pm Revision f0a9f021: remove old ethernet tester, no longer needed or working
- 11:23 pm Revision 6d0fa9ac: removed bit-rotted test harness
- 11:17 pm Revision addc1b74: remove old iad stuff
- 10:56 pm Revision 4172aa82: N210: added makefiles in for rev 4 versions (use LVDS)
- 09:42 pm Revision e7eb44d5: first cut at using lvds for adc pins
- 09:42 pm Revision e2eca54d: builds now
- 09:42 pm Revision 58fe6931: u2p-lvds: remove unused nets
- 09:42 pm Revision 9451cb63: u2p: FPGA internal termination on the clock line from ADC
05/27/2011
- 12:35 am Revision 79596926: u2p-rebase: go back to versions on next
- 12:31 am Revision e9a34b8b: u1p: need to declare wires
- 12:31 am Revision d0bfde42: u1p: do padding outside of gpif_rd, in packet_splitter
- 12:31 am Revision b51ef6e5: should split and reframe packets properly
- 12:31 am Revision 37cffdd3: u1p: vita packet generator for testing purposes
- 12:31 am Revision dcabd7f3: u1p: should fix underrun reporting
- 12:31 am Revision 552e81bf: u1p: implement a signal to indicate a partially full usb lut, to flush it
- 12:31 am Revision 08149d4c: u1p: connect frames per packet
- 12:31 am Revision 42561353: u1p: reset gpif
- 12:31 am Revision 56b133ea: B100: added some packet splitter debug pins, removed debug from GPIO port, swa...
- 12:31 am Revision f04a393d: u1p: use icarus verilog to find warnings
- 12:31 am Revision 39f96a47: u1p: fix bus widths and other warnings
- 12:31 am Revision fd2f7f33: u1p: revert change to address bus width
- 12:31 am Revision 262c6e92: u1p: added loopback and timed capability just like u1e
- 12:31 am Revision f5ef9116: u1p: pass tx status/error packets back through GPIF over the response channel ...
- 12:31 am Revision ac3e42d1: u1p: gpif-to-fx2 path should now handle arbitrary sized packets, up to 2KB
- 12:31 am Revision a4dc4a53: u1p: use 18 bit fifos and use full size of a block ram in the tx path
- 12:31 am Revision d71f8599: u1p:wr testbench
- 12:31 am Revision a2764a78: u1p: modify dsp_framer36 to allow it to skip the udp prot eng headers.
- This way it works with u1e, u1p, as well as u2/u2p
- 12:31 am Revision b8f5df99: u1p: unused signals
- 12:31 am Revision 9fe53488: u1p: debug pins
- 12:31 am Revision df88b4a5: u1p: modernize, fix warnings, debug pins
- 12:31 am Revision 8c8f38b0: u1p: add new file to build
- 12:31 am Revision 88cc06c1: u1p: better way of reframing the packets
- 12:31 am Revision 3a244ca4: successful test
- 12:31 am Revision 9ff35c8e: give response packets the same format as tx packets
- 12:31 am Revision 8f78482c: fixed length command packets
- 12:31 am Revision 0ce67c4b: pad out packets to a minimum length
- 12:31 am Revision 61ace1e0: u1p: added debug0, debug1 for GPIF debugging
- 12:31 am Revision 65ee9c7a: Fixed I2C pin names.
- 12:31 am Revision e7e51ee8: I2C slave address decoding for 16-bit dw instead of 32-bit
- 12:31 am Revision 9515a3a8: select bus is 2 bits wide
- 12:31 am Revision 5772aa4b: modernize the make files, it now compiles. not tested.
- 12:31 am Revision 9136be22: u1p: catch up with all the recent u1e changes
- 12:31 am Revision a24962fc: u1p: remove extram from Makefile
- 12:31 am Revision 40856137: u1p: add clear ports to gpif, not hooked up yet
- 12:31 am Revision a9f3336e: add padding into gpif response path
- 12:31 am Revision 7e7e329a: Use the 4th LED which is shared on the cfg_init_b pin
- 12:31 am Revision cf69f2b3: copied over from u1e, most pins hooked up.
- 12:31 am Revision e25f67d5: skeleton
- 12:31 am Revision 014ea687: gpif skeletons
- 12:31 am Revision 2d67e145: progress on gpif interface
- 12:31 am Revision 900f8cd5: added a loopback control port, will do full wishbone interface later
- 12:31 am Revision 038ea250: hook up flow control pins
- 12:31 am Revision e55e1540: use vita_tx_chain top level block
- 12:31 am Revision 8e6bbbbc: redone gpif interface to match nick's new spec
- 12:31 am Revision 24f8740e: old and unused
- 12:31 am Revision 955572c4: constrain the gpif clock
- 12:31 am Revision 92a608b2: send reset to the gpif
- 12:31 am Revision 294b8a28: fix ctrl/resp path to pass all 16 bits of data instead of the bottom bit
- typos fixed, everything is connected now, should just have off-by-1 error
lots of debug pins added - 12:31 am Revision 6f19b5f9: not used
- 12:31 am Revision d3f97446: fifo to wb should be functionally complete, needs testing
- 12:31 am Revision cde50d7a: put gpio back in
- 12:31 am Revision af9c419e: first steps to a command packet handler for u1+
- 12:31 am Revision 6f172696: copied over from other repo. Beginnings of a skeleton fpga image for USRP1-Plus
- 12:31 am Revision 020df898: compiles now
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