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Status open is is not closed all New Assigned Resolved Feedback Closed Rejected Monitor Received Rework (at CM) PendingShipment PendingCustomerUnits Project is is not fpga public uhd usrpe1xx Tracker is is not Bug Feature Support RMA Priority is is not Low Normal High Urgent Immediate Assignee is is not none all Alex Ruffell Ben Hilburn Ian Buckley Jason Abele John Malsbury Josh Blum Matt Ettus Nick Corgan Nick Foster Patrick Sisterhen Philip Balister Thomas Tsou Author is is not Alex Ruffell Ben Hilburn Ian Buckley Jason Abele John Malsbury Josh Blum Matt Ettus Nick Corgan Nick Foster Patrick Sisterhen Philip Balister Thomas Tsou Assignee's role is is not none all Manager Developer Reporter Subject contains doesn't contain Created less than days ago more than days ago days ago today this week days Updated less than days ago more than days ago days ago today this week days Start date in less than in more than in today this week less than days ago more than days ago days ago days Due date in less than in more than in today this week less than days ago more than days ago days ago days Estimated time is >= <= none all % Done is >= <= none all

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	#	Project	Tracker	Status	Priority	Subject	Assignee	Updated
	596	fpga	Bug	Assigned	Normal	ram_2port.v flopping order	Matt Ettus	08/24/2011 10:43 pm
	595	fpga	Bug	Assigned	Normal	fifo_2clock_cascade reset	Matt Ettus	08/24/2011 10:42 pm

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